STM32F37 Standard Peripheral bibliotheek  1.0
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stm32f37x_rcc.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F37X_RCC_H
31 #define __STM32F37X_RCC_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f37x.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
50 typedef struct
51 {
52  uint32_t SYSCLK_Frequency;
53  uint32_t HCLK_Frequency;
54  uint32_t PCLK1_Frequency;
55  uint32_t PCLK2_Frequency;
56  uint32_t ADCCLK_Frequency;
57  uint32_t SDADCCLK_Frequency;
58  uint32_t CECCLK_Frequency;
59  uint32_t I2C1CLK_Frequency;
60  uint32_t I2C2CLK_Frequency;
61  uint32_t USART1CLK_Frequency;
62  uint32_t USART2CLK_Frequency;
63  uint32_t USART3CLK_Frequency;
65 
66 /* Exported constants --------------------------------------------------------*/
67 
76 #define RCC_HSE_OFF ((uint8_t)0x00)
77 #define RCC_HSE_ON ((uint8_t)0x01)
78 #define RCC_HSE_Bypass ((uint8_t)0x05)
79 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
80  ((HSE) == RCC_HSE_Bypass))
81 
90 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
91 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
92 
93 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
94  ((SOURCE) == RCC_PLLSource_PREDIV1))
95 
103 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
104 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
105 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
106 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
107 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
108 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
109 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
110 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
111 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
112 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
113 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
114 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
115 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
116 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
117 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
118 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
119  ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
120  ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
121  ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
122  ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
123  ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
124  ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
125  ((MUL) == RCC_PLLMul_16))
126 
133 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
134 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
135 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
136 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
137 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
138 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
139 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
140 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
141 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
142 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
143 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
144 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
145 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
146 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
147 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
148 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
149 
150 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
151  ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
152  ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
153  ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
154  ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
155  ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
156  ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
157  ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
158 
166 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
167 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
168 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
169 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
170  ((SOURCE) == RCC_SYSCLKSource_HSE) || \
171  ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
172 
180 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
181 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
182 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
183 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
184 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
185 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
186 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
187 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
188 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
189 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
190  ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
191  ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
192  ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
193  ((HCLK) == RCC_SYSCLK_Div512))
194 
202 #define RCC_HCLK_Div1 RCC_CFGR_PPRE1_DIV1
203 #define RCC_HCLK_Div2 RCC_CFGR_PPRE1_DIV2
204 #define RCC_HCLK_Div4 RCC_CFGR_PPRE1_DIV4
205 #define RCC_HCLK_Div8 RCC_CFGR_PPRE1_DIV8
206 #define RCC_HCLK_Div16 RCC_CFGR_PPRE1_DIV16
207 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
208  ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
209  ((PCLK) == RCC_HCLK_Div16))
210 
218 #define RCC_PCLK2_Div2 ((uint32_t)0x00000000)
219 #define RCC_PCLK2_Div4 ((uint32_t)0x00004000)
220 #define RCC_PCLK2_Div6 ((uint32_t)0x00008000)
221 #define RCC_PCLK2_Div8 ((uint32_t)0x0000C000)
222 
223 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_PCLK2_Div2) || ((ADCCLK) == RCC_PCLK2_Div4) || \
224  ((ADCCLK) == RCC_PCLK2_Div6) || ((ADCCLK) == RCC_PCLK2_Div8))
225 
234 #define RCC_SDADCCLK_SYSCLK_Div2 ((uint32_t)0x80000000)
235 #define RCC_SDADCCLK_SYSCLK_Div4 ((uint32_t)0x88000000)
236 #define RCC_SDADCCLK_SYSCLK_Div6 ((uint32_t)0x90000000)
237 #define RCC_SDADCCLK_SYSCLK_Div8 ((uint32_t)0x98000000)
238 #define RCC_SDADCCLK_SYSCLK_Div10 ((uint32_t)0xA0000000)
239 #define RCC_SDADCCLK_SYSCLK_Div12 ((uint32_t)0xA8000000)
240 #define RCC_SDADCCLK_SYSCLK_Div14 ((uint32_t)0xB0000000)
241 #define RCC_SDADCCLK_SYSCLK_Div16 ((uint32_t)0xB8000000)
242 #define RCC_SDADCCLK_SYSCLK_Div20 ((uint32_t)0xC0000000)
243 #define RCC_SDADCCLK_SYSCLK_Div24 ((uint32_t)0xC8000000)
244 #define RCC_SDADCCLK_SYSCLK_Div28 ((uint32_t)0xD0000000)
245 #define RCC_SDADCCLK_SYSCLK_Div32 ((uint32_t)0xD8000000)
246 #define RCC_SDADCCLK_SYSCLK_Div36 ((uint32_t)0xE0000000)
247 #define RCC_SDADCCLK_SYSCLK_Div40 ((uint32_t)0xE8000000)
248 #define RCC_SDADCCLK_SYSCLK_Div44 ((uint32_t)0xF0000000)
249 #define RCC_SDADCCLK_SYSCLK_Div48 ((uint32_t)0xF8000000)
250 
251 #define IS_RCC_SDADCCLK(SDADCCLK) (((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div2) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div4) || \
252  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div6) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div8) || \
253  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div10) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div12) || \
254  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div14) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div16) || \
255  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div20) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div24) || \
256  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div28) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div32) || \
257  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div36) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div40) || \
258  ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div44) || ((SDADCCLK) == RCC_SDADCCLK_SYSCLK_Div48))
259 
267 #define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
268 #define RCC_CECCLK_LSE RCC_CFGR3_CECSW
269 
270 #define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
271 
280 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
281 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
282 
283 #define RCC_I2C2CLK_HSI ((uint32_t)0x10000000)
284 #define RCC_I2C2CLK_SYSCLK ((uint32_t)0x10000020)
285 
286 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK) || \
287  ((I2CCLK) == RCC_I2C2CLK_HSI) || ((I2CCLK) == RCC_I2C2CLK_SYSCLK))
288 
297 #define RCC_USART1CLK_PCLK ((uint32_t)0x10000000)
298 #define RCC_USART1CLK_SYSCLK ((uint32_t)0x10000001)
299 #define RCC_USART1CLK_LSE ((uint32_t)0x10000002)
300 #define RCC_USART1CLK_HSI ((uint32_t)0x10000003)
301 
302 #define RCC_USART2CLK_PCLK ((uint32_t)0x20000000)
303 #define RCC_USART2CLK_SYSCLK ((uint32_t)0x20010000)
304 #define RCC_USART2CLK_LSE ((uint32_t)0x20020000)
305 #define RCC_USART2CLK_HSI ((uint32_t)0x20030000)
306 
307 #define RCC_USART3CLK_PCLK ((uint32_t)0x30000000)
308 #define RCC_USART3CLK_SYSCLK ((uint32_t)0x30040000)
309 #define RCC_USART3CLK_LSE ((uint32_t)0x30080000)
310 #define RCC_USART3CLK_HSI ((uint32_t)0x300C0000)
311 
312 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
313  ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI) ||\
314  ((USARTCLK) == RCC_USART2CLK_PCLK) || ((USARTCLK) == RCC_USART2CLK_SYSCLK) || \
315  ((USARTCLK) == RCC_USART2CLK_LSE) || ((USARTCLK) == RCC_USART2CLK_HSI) || \
316  ((USARTCLK) == RCC_USART3CLK_PCLK) || ((USARTCLK) == RCC_USART3CLK_SYSCLK) || \
317  ((USARTCLK) == RCC_USART3CLK_LSE) || ((USARTCLK) == RCC_USART3CLK_HSI))
318 
327 #define RCC_IT_LSIRDY ((uint8_t)0x01)
328 #define RCC_IT_LSERDY ((uint8_t)0x02)
329 #define RCC_IT_HSIRDY ((uint8_t)0x04)
330 #define RCC_IT_HSERDY ((uint8_t)0x08)
331 #define RCC_IT_PLLRDY ((uint8_t)0x10)
332 #define RCC_IT_CSS ((uint8_t)0x80)
333 
334 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
335 
336 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
337  ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
338  ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_CSS))
339 
340 
341 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
342 
351 #define RCC_LSE_OFF ((uint32_t)0x00000000)
352 #define RCC_LSE_ON RCC_BDCR_LSEON
353 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
354 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
355  ((LSE) == RCC_LSE_Bypass))
356 
364 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
365 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
366 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
367 
368 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
369  ((SOURCE) == RCC_RTCCLKSource_LSI) || \
370  ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
371 
379 #define RCC_LSEDrive_Low ((uint32_t)0x00000000)
380 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
381 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
382 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV
383 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
384  ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
385 
393 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
394 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
395 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
396 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
397 #define RCC_AHBPeriph_GPIOE RCC_AHBENR_GPIOEEN
398 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
399 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
400 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
401 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
402 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
403 #define RCC_AHBPeriph_DMA2 RCC_AHBENR_DMA2EN
404 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
405 
406 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFA8) == 0x00) && ((PERIPH) != 0x00))
407 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFE81FFFF) == 0x00) && ((PERIPH) != 0x00))
408 
417 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
418 #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
419 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
420 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
421 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
422 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
423 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
424 #define RCC_APB2Periph_TIM19 RCC_APB2ENR_TIM19EN
425 #define RCC_APB2Periph_SDADC1 RCC_APB2ENR_SDADC1EN
426 #define RCC_APB2Periph_SDADC2 RCC_APB2ENR_SDADC2EN
427 #define RCC_APB2Periph_SDADC3 RCC_APB2ENR_SDADC3EN
428 
429 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xF8F08DFE) == 0x00) && ((PERIPH) != 0x00))
430 
438 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
439 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
440 #define RCC_APB1Periph_TIM4 RCC_APB1ENR_TIM4EN
441 #define RCC_APB1Periph_TIM5 RCC_APB1ENR_TIM5EN
442 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
443 #define RCC_APB1Periph_TIM7 RCC_APB1ENR_TIM7EN
444 #define RCC_APB1Periph_TIM12 RCC_APB1ENR_TIM12EN
445 #define RCC_APB1Periph_TIM13 RCC_APB1ENR_TIM13EN
446 #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
447 #define RCC_APB1Periph_TIM18 RCC_APB1ENR_TIM18EN
448 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
449 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
450 #define RCC_APB1Periph_SPI3 RCC_APB1ENR_SPI3EN
451 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
452 #define RCC_APB1Periph_USART3 RCC_APB1ENR_USART3EN
453 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
454 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
455 #define RCC_APB1Periph_USB RCC_APB1ENR_USBEN
456 #define RCC_APB1Periph_CAN1 RCC_APB1ENR_CAN1EN
457 #define RCC_APB1Periph_DAC2 RCC_APB1ENR_DAC2EN
458 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
459 #define RCC_APB1Periph_DAC1 RCC_APB1ENR_DAC1EN
460 #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN
461 
462 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x89193400) == 0x00) && ((PERIPH) != 0x00))
463 
471 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
472 #define RCC_MCOSource_LSI ((uint8_t)0x02)
473 #define RCC_MCOSource_LSE ((uint8_t)0x03)
474 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
475 #define RCC_MCOSource_HSI ((uint8_t)0x05)
476 #define RCC_MCOSource_HSE ((uint8_t)0x06)
477 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
478 
479 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) ||((SOURCE) == RCC_MCOSource_SYSCLK) ||\
480  ((SOURCE) == RCC_MCOSource_HSI) || ((SOURCE) == RCC_MCOSource_HSE) || \
481  ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE) || \
482  ((SOURCE) == RCC_MCOSource_PLLCLK_Div2))
483 
491  #define RCC_USBCLKSource_PLLCLK_1Div5 ((uint8_t)0x00)
492  #define RCC_USBCLKSource_PLLCLK_Div1 ((uint8_t)0x01)
493 
494  #define IS_RCC_USBCLK_SOURCE(SOURCE) (((SOURCE) == RCC_USBCLKSource_PLLCLK_1Div5) || \
495  ((SOURCE) == RCC_USBCLKSource_PLLCLK_Div1))
496 
503 #define RCC_FLAG_HSIRDY ((uint8_t)0x01)
504 #define RCC_FLAG_HSERDY ((uint8_t)0x11)
505 #define RCC_FLAG_PLLRDY ((uint8_t)0x19)
506 #define RCC_FLAG_LSERDY ((uint8_t)0x21)
507 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
508 #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
509 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
510 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
511 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
512 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
513 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
514 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
515 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
516 
517 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
518  ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
519  ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
520  ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
521  ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
522  ((FLAG) == RCC_FLAG_WWDGRST)|| ((FLAG) == RCC_FLAG_LPWRRST)|| \
523  ((FLAG) == RCC_FLAG_V18PWRRSTF))
524 
525 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
526 
535 /* Exported macro ------------------------------------------------------------*/
536 /* Exported functions ------------------------------------------------------- */
537 
538 /* Function used to set the RCC clock configuration to the default reset state */
539 void RCC_DeInit(void);
540 
541 /* Internal/external clocks, PLL, CSS and MCO configuration functions *********/
542 void RCC_HSEConfig(uint8_t RCC_HSE);
543 ErrorStatus RCC_WaitForHSEStartUp(void);
544 void RCC_AdjustHSICalibrationValue(uint8_t HSICalibrationValue);
545 void RCC_HSICmd(FunctionalState NewState);
546 void RCC_LSEConfig(uint32_t RCC_LSE);
547 void RCC_LSEDriveConfig(uint32_t RCC_LSEDrive);
548 void RCC_LSICmd(FunctionalState NewState);
549 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
550 void RCC_PLLCmd(FunctionalState NewState);
551 void RCC_PREDIV1Config(uint32_t RCC_PREDIV1_Div);
552 void RCC_ClockSecuritySystemCmd(FunctionalState NewState);
553 void RCC_MCOConfig(uint8_t RCC_MCOSource);
554 
555 /* System, AHB and APB busses clocks configuration functions ******************/
556 void RCC_SYSCLKConfig(uint32_t RCC_SYSCLKSource);
557 uint8_t RCC_GetSYSCLKSource(void);
558 void RCC_HCLKConfig(uint32_t RCC_SYSCLK);
559 void RCC_PCLK1Config(uint32_t RCC_HCLK);
560 void RCC_PCLK2Config(uint32_t RCC_HCLK);
561 void RCC_ADCCLKConfig(uint32_t RCC_PCLK2);
562 void RCC_SDADCCLKConfig(uint32_t RCC_SDADCCLK);
563 void RCC_CECCLKConfig(uint32_t RCC_CECCLK);
564 void RCC_I2CCLKConfig(uint32_t RCC_I2CCLK);
565 void RCC_USARTCLKConfig(uint32_t RCC_USARTCLK);
566 void RCC_USBCLKConfig(uint32_t RCC_USBCLKSource);
567 void RCC_GetClocksFreq(RCC_ClocksTypeDef* RCC_Clocks);
568 
569 /* Peripheral clocks configuration functions **********************************/
570 void RCC_RTCCLKConfig(uint32_t RCC_RTCCLKSource);
571 void RCC_RTCCLKCmd(FunctionalState NewState);
572 void RCC_BackupResetCmd(FunctionalState NewState);
573 
574 void RCC_AHBPeriphClockCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
575 void RCC_APB2PeriphClockCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
576 void RCC_APB1PeriphClockCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
577 
578 void RCC_AHBPeriphResetCmd(uint32_t RCC_AHBPeriph, FunctionalState NewState);
579 void RCC_APB2PeriphResetCmd(uint32_t RCC_APB2Periph, FunctionalState NewState);
580 void RCC_APB1PeriphResetCmd(uint32_t RCC_APB1Periph, FunctionalState NewState);
581 
582 /* Interrupts and flags management functions **********************************/
583 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);
584 FlagStatus RCC_GetFlagStatus(uint8_t RCC_FLAG);
585 void RCC_ClearFlag(void);
586 ITStatus RCC_GetITStatus(uint8_t RCC_IT);
587 void RCC_ClearITPendingBit(uint8_t RCC_IT);
588 
589 #ifdef __cplusplus
590 }
591 #endif
592 
593 #endif /* __STM32F37X_RCC_H */
594 
603 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/