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#define | DBGMCU_SLEEP DBGMCU_CR_DBG_SLEEP |
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#define | DBGMCU_STOP DBGMCU_CR_DBG_STOP |
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#define | DBGMCU_STANDBY DBGMCU_CR_DBG_STANDBY |
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#define | IS_DBGMCU_PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFF8) == 0x00) && ((PERIPH) != 0x00)) |
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#define | DBGMCU_TIM2_STOP DBGMCU_APB1_FZ_DBG_TIM2_STOP |
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#define | DBGMCU_TIM3_STOP DBGMCU_APB1_FZ_DBG_TIM3_STOP |
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#define | DBGMCU_TIM4_STOP DBGMCU_APB1_FZ_DBG_TIM4_STOP |
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#define | DBGMCU_TIM5_STOP DBGMCU_APB1_FZ_DBG_TIM5_STOP |
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#define | DBGMCU_TIM6_STOP DBGMCU_APB1_FZ_DBG_TIM6_STOP |
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#define | DBGMCU_TIM7_STOP DBGMCU_APB1_FZ_DBG_TIM7_STOP |
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#define | DBGMCU_TIM12_STOP DBGMCU_APB1_FZ_DBG_TIM12_STOP |
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#define | DBGMCU_TIM13_STOP DBGMCU_APB1_FZ_DBG_TIM13_STOP |
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#define | DBGMCU_TIM14_STOP DBGMCU_APB1_FZ_DBG_TIM14_STOP |
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#define | DBGMCU_TIM18_STOP DBGMCU_APB1_FZ_DBG_TIM18_STOP |
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#define | DBGMCU_RTC_STOP DBGMCU_APB1_FZ_DBG_RTC_STOP |
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#define | DBGMCU_WWDG_STOP DBGMCU_APB1_FZ_DBG_WWDG_STOP |
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#define | DBGMCU_IWDG_STOP DBGMCU_APB1_FZ_DBG_IWDG_STOP |
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#define | DBGMCU_I2C1_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C1_SMBUS_TIMEOUT |
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#define | DBGMCU_I2C2_SMBUS_TIMEOUT DBGMCU_APB1_FZ_DBG_I2C2_SMBUS_TIMEOUT |
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#define | DBGMCU_CAN1_STOP DBGMCU_APB1_FZ_DBG_CAN1_STOP |
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#define | IS_DBGMCU_APB1PERIPH(PERIPH) ((((PERIPH) & 0xFD9FE000) == 0x00) && ((PERIPH) != 0x00)) |
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#define | DBGMCU_TIM15_STOP DBGMCU_APB2_FZ_DBG_TIM15_STOP |
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#define | DBGMCU_TIM16_STOP DBGMCU_APB2_FZ_DBG_TIM16_STOP |
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#define | DBGMCU_TIM17_STOP DBGMCU_APB2_FZ_DBG_TIM17_STOP |
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#define | DBGMCU_TIM19_STOP DBGMCU_APB2_FZ_DBG_TIM19_STOP |
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#define | IS_DBGMCU_APB2PERIPH(PERIPH) ((((PERIPH) & 0xFFFFFFC3) == 0x00) && ((PERIPH) != 0x00)) |
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