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#define | CR1_SPE_Set ((uint16_t)0x0040) |
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#define | CR1_SPE_Reset ((uint16_t)0xFFBF) |
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#define | I2SCFGR_I2SE_Set ((uint16_t)0x0400) |
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#define | I2SCFGR_I2SE_Reset ((uint16_t)0xFBFF) |
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#define | CR1_CRCNext_Set ((uint16_t)0x1000) |
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#define | CR1_CRCEN_Set ((uint16_t)0x2000) |
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#define | CR1_CRCEN_Reset ((uint16_t)0xDFFF) |
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#define | CR2_SSOE_Set ((uint16_t)0x0004) |
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#define | CR2_SSOE_Reset ((uint16_t)0xFFFB) |
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#define | CR1_CLEAR_Mask ((uint16_t)0x3040) |
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#define | I2SCFGR_CLEAR_Mask ((uint16_t)0xF040) |
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#define | SPI_Mode_Select ((uint16_t)0xF7FF) |
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#define | I2S_Mode_Select ((uint16_t)0x0800) |
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#define | I2S2_CLOCK_SRC ((uint32_t)(0x00020000)) |
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#define | I2S3_CLOCK_SRC ((uint32_t)(0x00040000)) |
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#define | I2S_MUL_MASK ((uint32_t)(0x0000F000)) |
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#define | I2S_DIV_MASK ((uint32_t)(0x000000F0)) |
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