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#define | SDIO_OFFSET (SDIO_BASE - PERIPH_BASE) |
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#define | CLKCR_OFFSET (SDIO_OFFSET + 0x04) |
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#define | CLKEN_BitNumber 0x08 |
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#define | CLKCR_CLKEN_BB (PERIPH_BB_BASE + (CLKCR_OFFSET * 32) + (CLKEN_BitNumber * 4)) |
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#define | CMD_OFFSET (SDIO_OFFSET + 0x0C) |
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#define | SDIOSUSPEND_BitNumber 0x0B |
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#define | CMD_SDIOSUSPEND_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (SDIOSUSPEND_BitNumber * 4)) |
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#define | ENCMDCOMPL_BitNumber 0x0C |
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#define | CMD_ENCMDCOMPL_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ENCMDCOMPL_BitNumber * 4)) |
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#define | NIEN_BitNumber 0x0D |
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#define | CMD_NIEN_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (NIEN_BitNumber * 4)) |
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#define | ATACMD_BitNumber 0x0E |
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#define | CMD_ATACMD_BB (PERIPH_BB_BASE + (CMD_OFFSET * 32) + (ATACMD_BitNumber * 4)) |
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#define | DCTRL_OFFSET (SDIO_OFFSET + 0x2C) |
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#define | DMAEN_BitNumber 0x03 |
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#define | DCTRL_DMAEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (DMAEN_BitNumber * 4)) |
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#define | RWSTART_BitNumber 0x08 |
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#define | DCTRL_RWSTART_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTART_BitNumber * 4)) |
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#define | RWSTOP_BitNumber 0x09 |
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#define | DCTRL_RWSTOP_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWSTOP_BitNumber * 4)) |
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#define | RWMOD_BitNumber 0x0A |
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#define | DCTRL_RWMOD_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (RWMOD_BitNumber * 4)) |
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#define | SDIOEN_BitNumber 0x0B |
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#define | DCTRL_SDIOEN_BB (PERIPH_BB_BASE + (DCTRL_OFFSET * 32) + (SDIOEN_BitNumber * 4)) |
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#define | CLKCR_CLEAR_MASK ((uint32_t)0xFFFF8100) |
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#define | PWR_PWRCTRL_MASK ((uint32_t)0xFFFFFFFC) |
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#define | DCTRL_CLEAR_MASK ((uint32_t)0xFFFFFF08) |
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#define | CMD_CLEAR_MASK ((uint32_t)0xFFFFF800) |
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#define | SDIO_RESP_ADDR ((uint32_t)(SDIO_BASE + 0x14)) |
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