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#define | CCR_ENABLE_Set ((uint32_t)0x00000001) |
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#define | CCR_ENABLE_Reset ((uint32_t)0xFFFFFFFE) |
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#define | DMA1_Channel1_IT_Mask ((uint32_t)0x0000000F) |
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#define | DMA1_Channel2_IT_Mask ((uint32_t)0x000000F0) |
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#define | DMA1_Channel3_IT_Mask ((uint32_t)0x00000F00) |
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#define | DMA1_Channel4_IT_Mask ((uint32_t)0x0000F000) |
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#define | DMA1_Channel5_IT_Mask ((uint32_t)0x000F0000) |
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#define | DMA1_Channel6_IT_Mask ((uint32_t)0x00F00000) |
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#define | DMA1_Channel7_IT_Mask ((uint32_t)0x0F000000) |
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#define | DMA2_Channel1_IT_Mask ((uint32_t)0x0000000F) |
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#define | DMA2_Channel2_IT_Mask ((uint32_t)0x000000F0) |
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#define | DMA2_Channel3_IT_Mask ((uint32_t)0x00000F00) |
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#define | DMA2_Channel4_IT_Mask ((uint32_t)0x0000F000) |
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#define | DMA2_Channel5_IT_Mask ((uint32_t)0x000F0000) |
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#define | FLAG_Mask ((uint32_t)0x10000000) |
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#define | CCR_CLEAR_Mask ((uint32_t)0xFFFF800F) |
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