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#define | MCR_INRQ ((uint32_t)0x00000001) /* Initialization request */ |
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#define | MCR_SLEEP ((uint32_t)0x00000002) /* Sleep mode request */ |
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#define | MCR_TXFP ((uint32_t)0x00000004) /* Transmit FIFO priority */ |
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#define | MCR_RFLM ((uint32_t)0x00000008) /* Receive FIFO locked mode */ |
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#define | MCR_NART ((uint32_t)0x00000010) /* No automatic retransmission */ |
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#define | MCR_AWUM ((uint32_t)0x00000020) /* Automatic wake up mode */ |
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#define | MCR_ABOM ((uint32_t)0x00000040) /* Automatic bus-off management */ |
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#define | MCR_TTCM ((uint32_t)0x00000080) /* time triggered communication */ |
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#define | MCR_RESET ((uint32_t)0x00008000) /* time triggered communication */ |
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#define | MCR_DBF ((uint32_t)0x00010000) /* software master reset */ |
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#define | MSR_INAK ((uint32_t)0x00000001) /* Initialization acknowledge */ |
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#define | MSR_WKUI ((uint32_t)0x00000008) /* Wake-up interrupt */ |
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#define | MSR_SLAKI ((uint32_t)0x00000010) /* Sleep acknowledge interrupt */ |
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#define | TSR_RQCP0 ((uint32_t)0x00000001) /* Request completed mailbox0 */ |
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#define | TSR_TXOK0 ((uint32_t)0x00000002) /* Transmission OK of mailbox0 */ |
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#define | TSR_ABRQ0 ((uint32_t)0x00000080) /* Abort request for mailbox0 */ |
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#define | TSR_RQCP1 ((uint32_t)0x00000100) /* Request completed mailbox1 */ |
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#define | TSR_TXOK1 ((uint32_t)0x00000200) /* Transmission OK of mailbox1 */ |
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#define | TSR_ABRQ1 ((uint32_t)0x00008000) /* Abort request for mailbox1 */ |
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#define | TSR_RQCP2 ((uint32_t)0x00010000) /* Request completed mailbox2 */ |
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#define | TSR_TXOK2 ((uint32_t)0x00020000) /* Transmission OK of mailbox2 */ |
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#define | TSR_ABRQ2 ((uint32_t)0x00800000) /* Abort request for mailbox2 */ |
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#define | TSR_TME0 ((uint32_t)0x04000000) /* Transmit mailbox 0 empty */ |
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#define | TSR_TME1 ((uint32_t)0x08000000) /* Transmit mailbox 1 empty */ |
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#define | TSR_TME2 ((uint32_t)0x10000000) /* Transmit mailbox 2 empty */ |
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#define | RF0R_FULL0 ((uint32_t)0x00000008) /* FIFO 0 full */ |
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#define | RF0R_FOVR0 ((uint32_t)0x00000010) /* FIFO 0 overrun */ |
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#define | RF0R_RFOM0 ((uint32_t)0x00000020) /* Release FIFO 0 output mailbox */ |
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#define | RF1R_FULL1 ((uint32_t)0x00000008) /* FIFO 1 full */ |
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#define | RF1R_FOVR1 ((uint32_t)0x00000010) /* FIFO 1 overrun */ |
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#define | RF1R_RFOM1 ((uint32_t)0x00000020) /* Release FIFO 1 output mailbox */ |
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#define | ESR_EWGF ((uint32_t)0x00000001) /* Error warning flag */ |
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#define | ESR_EPVF ((uint32_t)0x00000002) /* Error passive flag */ |
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#define | ESR_BOFF ((uint32_t)0x00000004) /* Bus-off flag */ |
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#define | TMIDxR_TXRQ ((uint32_t)0x00000001) /* Transmit mailbox request */ |
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#define | FMR_FINIT ((uint32_t)0x00000001) /* Filter init mode */ |
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#define | INAK_TimeOut ((uint32_t)0x0000FFFF) |
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#define | SLAK_TimeOut ((uint32_t)0x0000FFFF) |
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