STM32F0 Standard Peripheral bibliotheek  1.0
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stm32f0xx_tim.h
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1 
29 /* Define to prevent recursive inclusion -------------------------------------*/
30 #ifndef __STM32F0XX_TIM_H
31 #define __STM32F0XX_TIM_H
32 
33 #ifdef __cplusplus
34  extern "C" {
35 #endif
36 
37 /* Includes ------------------------------------------------------------------*/
38 #include "stm32f0xx.h"
39 
48 /* Exported types ------------------------------------------------------------*/
49 
55 typedef struct
56 {
57  uint16_t TIM_Prescaler;
60  uint16_t TIM_CounterMode;
63  uint32_t TIM_Period;
67  uint16_t TIM_ClockDivision;
70  uint8_t TIM_RepetitionCounter;
79 
84 typedef struct
85 {
86  uint16_t TIM_OCMode;
89  uint16_t TIM_OutputState;
92  uint16_t TIM_OutputNState;
96  uint32_t TIM_Pulse;
100  uint16_t TIM_OCPolarity;
103  uint16_t TIM_OCNPolarity;
107  uint16_t TIM_OCIdleState;
111  uint16_t TIM_OCNIdleState;
115 
120 typedef struct
121 {
122 
123  uint16_t TIM_Channel;
126  uint16_t TIM_ICPolarity;
129  uint16_t TIM_ICSelection;
132  uint16_t TIM_ICPrescaler;
135  uint16_t TIM_ICFilter;
138 
144 typedef struct
145 {
146 
147  uint16_t TIM_OSSRState;
150  uint16_t TIM_OSSIState;
153  uint16_t TIM_LOCKLevel;
156  uint16_t TIM_DeadTime;
160  uint16_t TIM_Break;
163  uint16_t TIM_BreakPolarity;
166  uint16_t TIM_AutomaticOutput;
169 
174 /* Exported constants --------------------------------------------------------*/
175 
176 
181 #define IS_TIM_ALL_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
182  ((PERIPH) == TIM2) || \
183  ((PERIPH) == TIM3) || \
184  ((PERIPH) == TIM6) || \
185  ((PERIPH) == TIM14)|| \
186  ((PERIPH) == TIM15)|| \
187  ((PERIPH) == TIM16)|| \
188  ((PERIPH) == TIM17))
189 
190 /* LIST1: TIM 1 */
191 #define IS_TIM_LIST1_PERIPH(PERIPH) ((PERIPH) == TIM1)
192 
193 /* LIST2: TIM 1, 15, 16 and 17 */
194 #define IS_TIM_LIST2_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
195  ((PERIPH) == TIM15)|| \
196  ((PERIPH) == TIM16)|| \
197  ((PERIPH) == TIM17))
198 
199 /* LIST3: TIM 1, 2 and 3 */
200 #define IS_TIM_LIST3_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
201  ((PERIPH) == TIM2) || \
202  ((PERIPH) == TIM3))
203 
204 /* LIST4: TIM 1, 2, 3, 14, 15, 16 and 17 */
205 #define IS_TIM_LIST4_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
206  ((PERIPH) == TIM2) || \
207  ((PERIPH) == TIM3) || \
208  ((PERIPH) == TIM14) || \
209  ((PERIPH) == TIM15)|| \
210  ((PERIPH) == TIM16)|| \
211  ((PERIPH) == TIM17))
212 
213 /* LIST4: TIM 1, 2, 3, 15, 16 and 17 */
214 #define IS_TIM_LIST5_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
215  ((PERIPH) == TIM2) || \
216  ((PERIPH) == TIM3) || \
217  ((PERIPH) == TIM15)|| \
218  ((PERIPH) == TIM16)|| \
219  ((PERIPH) == TIM17))
220 
221 /* LIST5: TIM 1, 2, 3 and 15 */
222 #define IS_TIM_LIST6_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
223  ((PERIPH) == TIM2) || \
224  ((PERIPH) == TIM3) || \
225  ((PERIPH) == TIM15))
226 
227 /* LIST7: TIM 1, 2, 3, 6 and 14 */
228 #define IS_TIM_LIST7_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
229  ((PERIPH) == TIM2) || \
230  ((PERIPH) == TIM3) || \
231  ((PERIPH) == TIM6) || \
232  ((PERIPH) == TIM14))
233 
234 /* LIST8: TIM 1, 2, 3 and 14 */
235 #define IS_TIM_LIST8_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
236  ((PERIPH) == TIM2) || \
237  ((PERIPH) == TIM3) || \
238  ((PERIPH) == TIM14))
239 
240 /* LIST9: TIM 1, 2, 3, 6 and 15 */
241 #define IS_TIM_LIST9_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
242  ((PERIPH) == TIM2) || \
243  ((PERIPH) == TIM3) || \
244  ((PERIPH) == TIM6) || \
245  ((PERIPH) == TIM15))
246 
247 /* LIST10: TIM 1, 2, 3, 6, 15, 16 and 17 */
248 #define IS_TIM_LIST10_PERIPH(PERIPH) (((PERIPH) == TIM1) || \
249  ((PERIPH) == TIM2) || \
250  ((PERIPH) == TIM3) || \
251  ((PERIPH) == TIM6) || \
252  ((PERIPH) == TIM15)|| \
253  ((PERIPH) == TIM16)|| \
254  ((PERIPH) == TIM17))
255 
256 /* LIST1: TIM 11 */
257 #define IS_TIM_LIST11_PERIPH(PERIPH) ((PERIPH) == TIM14)
258 
259 
268 #define TIM_OCMode_Timing ((uint16_t)0x0000)
269 #define TIM_OCMode_Active ((uint16_t)0x0010)
270 #define TIM_OCMode_Inactive ((uint16_t)0x0020)
271 #define TIM_OCMode_Toggle ((uint16_t)0x0030)
272 #define TIM_OCMode_PWM1 ((uint16_t)0x0060)
273 #define TIM_OCMode_PWM2 ((uint16_t)0x0070)
274 #define IS_TIM_OC_MODE(MODE) (((MODE) == TIM_OCMode_Timing) || \
275  ((MODE) == TIM_OCMode_Active) || \
276  ((MODE) == TIM_OCMode_Inactive) || \
277  ((MODE) == TIM_OCMode_Toggle)|| \
278  ((MODE) == TIM_OCMode_PWM1) || \
279  ((MODE) == TIM_OCMode_PWM2))
280 #define IS_TIM_OCM(MODE) (((MODE) == TIM_OCMode_Timing) || \
281  ((MODE) == TIM_OCMode_Active) || \
282  ((MODE) == TIM_OCMode_Inactive) || \
283  ((MODE) == TIM_OCMode_Toggle)|| \
284  ((MODE) == TIM_OCMode_PWM1) || \
285  ((MODE) == TIM_OCMode_PWM2) || \
286  ((MODE) == TIM_ForcedAction_Active) || \
287  ((MODE) == TIM_ForcedAction_InActive))
288 
296 #define TIM_OPMode_Single ((uint16_t)0x0008)
297 #define TIM_OPMode_Repetitive ((uint16_t)0x0000)
298 #define IS_TIM_OPM_MODE(MODE) (((MODE) == TIM_OPMode_Single) || \
299  ((MODE) == TIM_OPMode_Repetitive))
300 
308 #define TIM_Channel_1 ((uint16_t)0x0000)
309 #define TIM_Channel_2 ((uint16_t)0x0004)
310 #define TIM_Channel_3 ((uint16_t)0x0008)
311 #define TIM_Channel_4 ((uint16_t)0x000C)
312 
313 #define IS_TIM_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
314  ((CHANNEL) == TIM_Channel_2) || \
315  ((CHANNEL) == TIM_Channel_3) || \
316  ((CHANNEL) == TIM_Channel_4))
317 #define IS_TIM_COMPLEMENTARY_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
318  ((CHANNEL) == TIM_Channel_2) || \
319  ((CHANNEL) == TIM_Channel_3))
320 #define IS_TIM_PWMI_CHANNEL(CHANNEL) (((CHANNEL) == TIM_Channel_1) || \
321  ((CHANNEL) == TIM_Channel_2))
322 
331 #define TIM_CKD_DIV1 ((uint16_t)0x0000)
332 #define TIM_CKD_DIV2 ((uint16_t)0x0100)
333 #define TIM_CKD_DIV4 ((uint16_t)0x0200)
334 #define IS_TIM_CKD_DIV(DIV) (((DIV) == TIM_CKD_DIV1) || \
335  ((DIV) == TIM_CKD_DIV2) || \
336  ((DIV) == TIM_CKD_DIV4))
337 
345 #define TIM_CounterMode_Up ((uint16_t)0x0000)
346 #define TIM_CounterMode_Down ((uint16_t)0x0010)
347 #define TIM_CounterMode_CenterAligned1 ((uint16_t)0x0020)
348 #define TIM_CounterMode_CenterAligned2 ((uint16_t)0x0040)
349 #define TIM_CounterMode_CenterAligned3 ((uint16_t)0x0060)
350 #define IS_TIM_COUNTER_MODE(MODE) (((MODE) == TIM_CounterMode_Up) || \
351  ((MODE) == TIM_CounterMode_Down) || \
352  ((MODE) == TIM_CounterMode_CenterAligned1) || \
353  ((MODE) == TIM_CounterMode_CenterAligned2) || \
354  ((MODE) == TIM_CounterMode_CenterAligned3))
355 
363 #define TIM_OCPolarity_High ((uint16_t)0x0000)
364 #define TIM_OCPolarity_Low ((uint16_t)0x0002)
365 #define IS_TIM_OC_POLARITY(POLARITY) (((POLARITY) == TIM_OCPolarity_High) || \
366  ((POLARITY) == TIM_OCPolarity_Low))
367 
375 #define TIM_OCNPolarity_High ((uint16_t)0x0000)
376 #define TIM_OCNPolarity_Low ((uint16_t)0x0008)
377 #define IS_TIM_OCN_POLARITY(POLARITY) (((POLARITY) == TIM_OCNPolarity_High) || \
378  ((POLARITY) == TIM_OCNPolarity_Low))
379 
387 #define TIM_OutputState_Disable ((uint16_t)0x0000)
388 #define TIM_OutputState_Enable ((uint16_t)0x0001)
389 #define IS_TIM_OUTPUT_STATE(STATE) (((STATE) == TIM_OutputState_Disable) || \
390  ((STATE) == TIM_OutputState_Enable))
391 
399 #define TIM_OutputNState_Disable ((uint16_t)0x0000)
400 #define TIM_OutputNState_Enable ((uint16_t)0x0004)
401 #define IS_TIM_OUTPUTN_STATE(STATE) (((STATE) == TIM_OutputNState_Disable) || \
402  ((STATE) == TIM_OutputNState_Enable))
403 
411 #define TIM_CCx_Enable ((uint16_t)0x0001)
412 #define TIM_CCx_Disable ((uint16_t)0x0000)
413 #define IS_TIM_CCX(CCX) (((CCX) == TIM_CCx_Enable) || \
414  ((CCX) == TIM_CCx_Disable))
415 
423 #define TIM_CCxN_Enable ((uint16_t)0x0004)
424 #define TIM_CCxN_Disable ((uint16_t)0x0000)
425 #define IS_TIM_CCXN(CCXN) (((CCXN) == TIM_CCxN_Enable) || \
426  ((CCXN) == TIM_CCxN_Disable))
427 
435 #define TIM_Break_Enable ((uint16_t)0x1000)
436 #define TIM_Break_Disable ((uint16_t)0x0000)
437 #define IS_TIM_BREAK_STATE(STATE) (((STATE) == TIM_Break_Enable) || \
438  ((STATE) == TIM_Break_Disable))
439 
447 #define TIM_BreakPolarity_Low ((uint16_t)0x0000)
448 #define TIM_BreakPolarity_High ((uint16_t)0x2000)
449 #define IS_TIM_BREAK_POLARITY(POLARITY) (((POLARITY) == TIM_BreakPolarity_Low) || \
450  ((POLARITY) == TIM_BreakPolarity_High))
451 
459 #define TIM_AutomaticOutput_Enable ((uint16_t)0x4000)
460 #define TIM_AutomaticOutput_Disable ((uint16_t)0x0000)
461 #define IS_TIM_AUTOMATIC_OUTPUT_STATE(STATE) (((STATE) == TIM_AutomaticOutput_Enable) || \
462  ((STATE) == TIM_AutomaticOutput_Disable))
463 
471 #define TIM_LOCKLevel_OFF ((uint16_t)0x0000)
472 #define TIM_LOCKLevel_1 ((uint16_t)0x0100)
473 #define TIM_LOCKLevel_2 ((uint16_t)0x0200)
474 #define TIM_LOCKLevel_3 ((uint16_t)0x0300)
475 #define IS_TIM_LOCK_LEVEL(LEVEL) (((LEVEL) == TIM_LOCKLevel_OFF) || \
476  ((LEVEL) == TIM_LOCKLevel_1) || \
477  ((LEVEL) == TIM_LOCKLevel_2) || \
478  ((LEVEL) == TIM_LOCKLevel_3))
479 
487 #define TIM_OSSIState_Enable ((uint16_t)0x0400)
488 #define TIM_OSSIState_Disable ((uint16_t)0x0000)
489 #define IS_TIM_OSSI_STATE(STATE) (((STATE) == TIM_OSSIState_Enable) || \
490  ((STATE) == TIM_OSSIState_Disable))
491 
499 #define TIM_OSSRState_Enable ((uint16_t)0x0800)
500 #define TIM_OSSRState_Disable ((uint16_t)0x0000)
501 #define IS_TIM_OSSR_STATE(STATE) (((STATE) == TIM_OSSRState_Enable) || \
502  ((STATE) == TIM_OSSRState_Disable))
503 
511 #define TIM_OCIdleState_Set ((uint16_t)0x0100)
512 #define TIM_OCIdleState_Reset ((uint16_t)0x0000)
513 #define IS_TIM_OCIDLE_STATE(STATE) (((STATE) == TIM_OCIdleState_Set) || \
514  ((STATE) == TIM_OCIdleState_Reset))
515 
523 #define TIM_OCNIdleState_Set ((uint16_t)0x0200)
524 #define TIM_OCNIdleState_Reset ((uint16_t)0x0000)
525 #define IS_TIM_OCNIDLE_STATE(STATE) (((STATE) == TIM_OCNIdleState_Set) || \
526  ((STATE) == TIM_OCNIdleState_Reset))
527 
535 #define TIM_ICPolarity_Rising ((uint16_t)0x0000)
536 #define TIM_ICPolarity_Falling ((uint16_t)0x0002)
537 #define TIM_ICPolarity_BothEdge ((uint16_t)0x000A)
538 #define IS_TIM_IC_POLARITY(POLARITY) (((POLARITY) == TIM_ICPolarity_Rising) || \
539  ((POLARITY) == TIM_ICPolarity_Falling)|| \
540  ((POLARITY) == TIM_ICPolarity_BothEdge))
541 
549 #define TIM_ICSelection_DirectTI ((uint16_t)0x0001)
551 #define TIM_ICSelection_IndirectTI ((uint16_t)0x0002)
553 #define TIM_ICSelection_TRC ((uint16_t)0x0003)
554 #define IS_TIM_IC_SELECTION(SELECTION) (((SELECTION) == TIM_ICSelection_DirectTI) || \
555  ((SELECTION) == TIM_ICSelection_IndirectTI) || \
556  ((SELECTION) == TIM_ICSelection_TRC))
557 
565 #define TIM_ICPSC_DIV1 ((uint16_t)0x0000)
566 #define TIM_ICPSC_DIV2 ((uint16_t)0x0004)
567 #define TIM_ICPSC_DIV4 ((uint16_t)0x0008)
568 #define TIM_ICPSC_DIV8 ((uint16_t)0x000C)
569 #define IS_TIM_IC_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ICPSC_DIV1) || \
570  ((PRESCALER) == TIM_ICPSC_DIV2) || \
571  ((PRESCALER) == TIM_ICPSC_DIV4) || \
572  ((PRESCALER) == TIM_ICPSC_DIV8))
573 
581 #define TIM_IT_Update ((uint16_t)0x0001)
582 #define TIM_IT_CC1 ((uint16_t)0x0002)
583 #define TIM_IT_CC2 ((uint16_t)0x0004)
584 #define TIM_IT_CC3 ((uint16_t)0x0008)
585 #define TIM_IT_CC4 ((uint16_t)0x0010)
586 #define TIM_IT_COM ((uint16_t)0x0020)
587 #define TIM_IT_Trigger ((uint16_t)0x0040)
588 #define TIM_IT_Break ((uint16_t)0x0080)
589 #define IS_TIM_IT(IT) ((((IT) & (uint16_t)0xFF00) == 0x0000) && ((IT) != 0x0000))
590 
591 #define IS_TIM_GET_IT(IT) (((IT) == TIM_IT_Update) || \
592  ((IT) == TIM_IT_CC1) || \
593  ((IT) == TIM_IT_CC2) || \
594  ((IT) == TIM_IT_CC3) || \
595  ((IT) == TIM_IT_CC4) || \
596  ((IT) == TIM_IT_COM) || \
597  ((IT) == TIM_IT_Trigger) || \
598  ((IT) == TIM_IT_Break))
599 
607 #define TIM_DMABase_CR1 ((uint16_t)0x0000)
608 #define TIM_DMABase_CR2 ((uint16_t)0x0001)
609 #define TIM_DMABase_SMCR ((uint16_t)0x0002)
610 #define TIM_DMABase_DIER ((uint16_t)0x0003)
611 #define TIM_DMABase_SR ((uint16_t)0x0004)
612 #define TIM_DMABase_EGR ((uint16_t)0x0005)
613 #define TIM_DMABase_CCMR1 ((uint16_t)0x0006)
614 #define TIM_DMABase_CCMR2 ((uint16_t)0x0007)
615 #define TIM_DMABase_CCER ((uint16_t)0x0008)
616 #define TIM_DMABase_CNT ((uint16_t)0x0009)
617 #define TIM_DMABase_PSC ((uint16_t)0x000A)
618 #define TIM_DMABase_ARR ((uint16_t)0x000B)
619 #define TIM_DMABase_RCR ((uint16_t)0x000C)
620 #define TIM_DMABase_CCR1 ((uint16_t)0x000D)
621 #define TIM_DMABase_CCR2 ((uint16_t)0x000E)
622 #define TIM_DMABase_CCR3 ((uint16_t)0x000F)
623 #define TIM_DMABase_CCR4 ((uint16_t)0x0010)
624 #define TIM_DMABase_BDTR ((uint16_t)0x0011)
625 #define TIM_DMABase_DCR ((uint16_t)0x0012)
626 #define TIM_DMABase_OR ((uint16_t)0x0013)
627 #define IS_TIM_DMA_BASE(BASE) (((BASE) == TIM_DMABase_CR1) || \
628  ((BASE) == TIM_DMABase_CR2) || \
629  ((BASE) == TIM_DMABase_SMCR) || \
630  ((BASE) == TIM_DMABase_DIER) || \
631  ((BASE) == TIM_DMABase_SR) || \
632  ((BASE) == TIM_DMABase_EGR) || \
633  ((BASE) == TIM_DMABase_CCMR1) || \
634  ((BASE) == TIM_DMABase_CCMR2) || \
635  ((BASE) == TIM_DMABase_CCER) || \
636  ((BASE) == TIM_DMABase_CNT) || \
637  ((BASE) == TIM_DMABase_PSC) || \
638  ((BASE) == TIM_DMABase_ARR) || \
639  ((BASE) == TIM_DMABase_RCR) || \
640  ((BASE) == TIM_DMABase_CCR1) || \
641  ((BASE) == TIM_DMABase_CCR2) || \
642  ((BASE) == TIM_DMABase_CCR3) || \
643  ((BASE) == TIM_DMABase_CCR4) || \
644  ((BASE) == TIM_DMABase_BDTR) || \
645  ((BASE) == TIM_DMABase_DCR) || \
646  ((BASE) == TIM_DMABase_OR))
647 
656 #define TIM_DMABurstLength_1Transfer ((uint16_t)0x0000)
657 #define TIM_DMABurstLength_2Transfers ((uint16_t)0x0100)
658 #define TIM_DMABurstLength_3Transfers ((uint16_t)0x0200)
659 #define TIM_DMABurstLength_4Transfers ((uint16_t)0x0300)
660 #define TIM_DMABurstLength_5Transfers ((uint16_t)0x0400)
661 #define TIM_DMABurstLength_6Transfers ((uint16_t)0x0500)
662 #define TIM_DMABurstLength_7Transfers ((uint16_t)0x0600)
663 #define TIM_DMABurstLength_8Transfers ((uint16_t)0x0700)
664 #define TIM_DMABurstLength_9Transfers ((uint16_t)0x0800)
665 #define TIM_DMABurstLength_10Transfers ((uint16_t)0x0900)
666 #define TIM_DMABurstLength_11Transfers ((uint16_t)0x0A00)
667 #define TIM_DMABurstLength_12Transfers ((uint16_t)0x0B00)
668 #define TIM_DMABurstLength_13Transfers ((uint16_t)0x0C00)
669 #define TIM_DMABurstLength_14Transfers ((uint16_t)0x0D00)
670 #define TIM_DMABurstLength_15Transfers ((uint16_t)0x0E00)
671 #define TIM_DMABurstLength_16Transfers ((uint16_t)0x0F00)
672 #define TIM_DMABurstLength_17Transfers ((uint16_t)0x1000)
673 #define TIM_DMABurstLength_18Transfers ((uint16_t)0x1100)
674 #define IS_TIM_DMA_LENGTH(LENGTH) (((LENGTH) == TIM_DMABurstLength_1Transfer) || \
675  ((LENGTH) == TIM_DMABurstLength_2Transfers) || \
676  ((LENGTH) == TIM_DMABurstLength_3Transfers) || \
677  ((LENGTH) == TIM_DMABurstLength_4Transfers) || \
678  ((LENGTH) == TIM_DMABurstLength_5Transfers) || \
679  ((LENGTH) == TIM_DMABurstLength_6Transfers) || \
680  ((LENGTH) == TIM_DMABurstLength_7Transfers) || \
681  ((LENGTH) == TIM_DMABurstLength_8Transfers) || \
682  ((LENGTH) == TIM_DMABurstLength_9Transfers) || \
683  ((LENGTH) == TIM_DMABurstLength_10Transfers) || \
684  ((LENGTH) == TIM_DMABurstLength_11Transfers) || \
685  ((LENGTH) == TIM_DMABurstLength_12Transfers) || \
686  ((LENGTH) == TIM_DMABurstLength_13Transfers) || \
687  ((LENGTH) == TIM_DMABurstLength_14Transfers) || \
688  ((LENGTH) == TIM_DMABurstLength_15Transfers) || \
689  ((LENGTH) == TIM_DMABurstLength_16Transfers) || \
690  ((LENGTH) == TIM_DMABurstLength_17Transfers) || \
691  ((LENGTH) == TIM_DMABurstLength_18Transfers))
692 
700 #define TIM_DMA_Update ((uint16_t)0x0100)
701 #define TIM_DMA_CC1 ((uint16_t)0x0200)
702 #define TIM_DMA_CC2 ((uint16_t)0x0400)
703 #define TIM_DMA_CC3 ((uint16_t)0x0800)
704 #define TIM_DMA_CC4 ((uint16_t)0x1000)
705 #define TIM_DMA_COM ((uint16_t)0x2000)
706 #define TIM_DMA_Trigger ((uint16_t)0x4000)
707 #define IS_TIM_DMA_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0x80FF) == 0x0000) && ((SOURCE) != 0x0000))
708 
717 #define TIM_ExtTRGPSC_OFF ((uint16_t)0x0000)
718 #define TIM_ExtTRGPSC_DIV2 ((uint16_t)0x1000)
719 #define TIM_ExtTRGPSC_DIV4 ((uint16_t)0x2000)
720 #define TIM_ExtTRGPSC_DIV8 ((uint16_t)0x3000)
721 #define IS_TIM_EXT_PRESCALER(PRESCALER) (((PRESCALER) == TIM_ExtTRGPSC_OFF) || \
722  ((PRESCALER) == TIM_ExtTRGPSC_DIV2) || \
723  ((PRESCALER) == TIM_ExtTRGPSC_DIV4) || \
724  ((PRESCALER) == TIM_ExtTRGPSC_DIV8))
725 
733 #define TIM_TS_ITR0 ((uint16_t)0x0000)
734 #define TIM_TS_ITR1 ((uint16_t)0x0010)
735 #define TIM_TS_ITR2 ((uint16_t)0x0020)
736 #define TIM_TS_ITR3 ((uint16_t)0x0030)
737 #define TIM_TS_TI1F_ED ((uint16_t)0x0040)
738 #define TIM_TS_TI1FP1 ((uint16_t)0x0050)
739 #define TIM_TS_TI2FP2 ((uint16_t)0x0060)
740 #define TIM_TS_ETRF ((uint16_t)0x0070)
741 #define IS_TIM_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
742  ((SELECTION) == TIM_TS_ITR1) || \
743  ((SELECTION) == TIM_TS_ITR2) || \
744  ((SELECTION) == TIM_TS_ITR3) || \
745  ((SELECTION) == TIM_TS_TI1F_ED) || \
746  ((SELECTION) == TIM_TS_TI1FP1) || \
747  ((SELECTION) == TIM_TS_TI2FP2) || \
748  ((SELECTION) == TIM_TS_ETRF))
749 #define IS_TIM_INTERNAL_TRIGGER_SELECTION(SELECTION) (((SELECTION) == TIM_TS_ITR0) || \
750  ((SELECTION) == TIM_TS_ITR1) || \
751  ((SELECTION) == TIM_TS_ITR2) || \
752  ((SELECTION) == TIM_TS_ITR3))
753 
761 #define TIM_TIxExternalCLK1Source_TI1 ((uint16_t)0x0050)
762 #define TIM_TIxExternalCLK1Source_TI2 ((uint16_t)0x0060)
763 #define TIM_TIxExternalCLK1Source_TI1ED ((uint16_t)0x0040)
764 
772 #define TIM_ExtTRGPolarity_Inverted ((uint16_t)0x8000)
773 #define TIM_ExtTRGPolarity_NonInverted ((uint16_t)0x0000)
774 #define IS_TIM_EXT_POLARITY(POLARITY) (((POLARITY) == TIM_ExtTRGPolarity_Inverted) || \
775  ((POLARITY) == TIM_ExtTRGPolarity_NonInverted))
776 
784 #define TIM_PSCReloadMode_Update ((uint16_t)0x0000)
785 #define TIM_PSCReloadMode_Immediate ((uint16_t)0x0001)
786 #define IS_TIM_PRESCALER_RELOAD(RELOAD) (((RELOAD) == TIM_PSCReloadMode_Update) || \
787  ((RELOAD) == TIM_PSCReloadMode_Immediate))
788 
796 #define TIM_ForcedAction_Active ((uint16_t)0x0050)
797 #define TIM_ForcedAction_InActive ((uint16_t)0x0040)
798 #define IS_TIM_FORCED_ACTION(ACTION) (((ACTION) == TIM_ForcedAction_Active) || \
799  ((ACTION) == TIM_ForcedAction_InActive))
800 
808 #define TIM_EncoderMode_TI1 ((uint16_t)0x0001)
809 #define TIM_EncoderMode_TI2 ((uint16_t)0x0002)
810 #define TIM_EncoderMode_TI12 ((uint16_t)0x0003)
811 #define IS_TIM_ENCODER_MODE(MODE) (((MODE) == TIM_EncoderMode_TI1) || \
812  ((MODE) == TIM_EncoderMode_TI2) || \
813  ((MODE) == TIM_EncoderMode_TI12))
814 
823 #define TIM_EventSource_Update ((uint16_t)0x0001)
824 #define TIM_EventSource_CC1 ((uint16_t)0x0002)
825 #define TIM_EventSource_CC2 ((uint16_t)0x0004)
826 #define TIM_EventSource_CC3 ((uint16_t)0x0008)
827 #define TIM_EventSource_CC4 ((uint16_t)0x0010)
828 #define TIM_EventSource_COM ((uint16_t)0x0020)
829 #define TIM_EventSource_Trigger ((uint16_t)0x0040)
830 #define TIM_EventSource_Break ((uint16_t)0x0080)
831 #define IS_TIM_EVENT_SOURCE(SOURCE) ((((SOURCE) & (uint16_t)0xFF00) == 0x0000) && ((SOURCE) != 0x0000))
832 
841 #define TIM_UpdateSource_Global ((uint16_t)0x0000)
844 #define TIM_UpdateSource_Regular ((uint16_t)0x0001)
845 #define IS_TIM_UPDATE_SOURCE(SOURCE) (((SOURCE) == TIM_UpdateSource_Global) || \
846  ((SOURCE) == TIM_UpdateSource_Regular))
847 
855 #define TIM_OCPreload_Enable ((uint16_t)0x0008)
856 #define TIM_OCPreload_Disable ((uint16_t)0x0000)
857 #define IS_TIM_OCPRELOAD_STATE(STATE) (((STATE) == TIM_OCPreload_Enable) || \
858  ((STATE) == TIM_OCPreload_Disable))
859 
867 #define TIM_OCFast_Enable ((uint16_t)0x0004)
868 #define TIM_OCFast_Disable ((uint16_t)0x0000)
869 #define IS_TIM_OCFAST_STATE(STATE) (((STATE) == TIM_OCFast_Enable) || \
870  ((STATE) == TIM_OCFast_Disable))
871 
880 #define TIM_OCClear_Enable ((uint16_t)0x0080)
881 #define TIM_OCClear_Disable ((uint16_t)0x0000)
882 #define IS_TIM_OCCLEAR_STATE(STATE) (((STATE) == TIM_OCClear_Enable) || \
883  ((STATE) == TIM_OCClear_Disable))
884 
892 #define TIM_TRGOSource_Reset ((uint16_t)0x0000)
893 #define TIM_TRGOSource_Enable ((uint16_t)0x0010)
894 #define TIM_TRGOSource_Update ((uint16_t)0x0020)
895 #define TIM_TRGOSource_OC1 ((uint16_t)0x0030)
896 #define TIM_TRGOSource_OC1Ref ((uint16_t)0x0040)
897 #define TIM_TRGOSource_OC2Ref ((uint16_t)0x0050)
898 #define TIM_TRGOSource_OC3Ref ((uint16_t)0x0060)
899 #define TIM_TRGOSource_OC4Ref ((uint16_t)0x0070)
900 #define IS_TIM_TRGO_SOURCE(SOURCE) (((SOURCE) == TIM_TRGOSource_Reset) || \
901  ((SOURCE) == TIM_TRGOSource_Enable) || \
902  ((SOURCE) == TIM_TRGOSource_Update) || \
903  ((SOURCE) == TIM_TRGOSource_OC1) || \
904  ((SOURCE) == TIM_TRGOSource_OC1Ref) || \
905  ((SOURCE) == TIM_TRGOSource_OC2Ref) || \
906  ((SOURCE) == TIM_TRGOSource_OC3Ref) || \
907  ((SOURCE) == TIM_TRGOSource_OC4Ref))
908 
916 #define TIM_SlaveMode_Reset ((uint16_t)0x0004)
917 #define TIM_SlaveMode_Gated ((uint16_t)0x0005)
918 #define TIM_SlaveMode_Trigger ((uint16_t)0x0006)
919 #define TIM_SlaveMode_External1 ((uint16_t)0x0007)
920 #define IS_TIM_SLAVE_MODE(MODE) (((MODE) == TIM_SlaveMode_Reset) || \
921  ((MODE) == TIM_SlaveMode_Gated) || \
922  ((MODE) == TIM_SlaveMode_Trigger) || \
923  ((MODE) == TIM_SlaveMode_External1))
924 
932 #define TIM_MasterSlaveMode_Enable ((uint16_t)0x0080)
933 #define TIM_MasterSlaveMode_Disable ((uint16_t)0x0000)
934 #define IS_TIM_MSM_STATE(STATE) (((STATE) == TIM_MasterSlaveMode_Enable) || \
935  ((STATE) == TIM_MasterSlaveMode_Disable))
936 
944 #define TIM_FLAG_Update ((uint16_t)0x0001)
945 #define TIM_FLAG_CC1 ((uint16_t)0x0002)
946 #define TIM_FLAG_CC2 ((uint16_t)0x0004)
947 #define TIM_FLAG_CC3 ((uint16_t)0x0008)
948 #define TIM_FLAG_CC4 ((uint16_t)0x0010)
949 #define TIM_FLAG_COM ((uint16_t)0x0020)
950 #define TIM_FLAG_Trigger ((uint16_t)0x0040)
951 #define TIM_FLAG_Break ((uint16_t)0x0080)
952 #define TIM_FLAG_CC1OF ((uint16_t)0x0200)
953 #define TIM_FLAG_CC2OF ((uint16_t)0x0400)
954 #define TIM_FLAG_CC3OF ((uint16_t)0x0800)
955 #define TIM_FLAG_CC4OF ((uint16_t)0x1000)
956 #define IS_TIM_GET_FLAG(FLAG) (((FLAG) == TIM_FLAG_Update) || \
957  ((FLAG) == TIM_FLAG_CC1) || \
958  ((FLAG) == TIM_FLAG_CC2) || \
959  ((FLAG) == TIM_FLAG_CC3) || \
960  ((FLAG) == TIM_FLAG_CC4) || \
961  ((FLAG) == TIM_FLAG_COM) || \
962  ((FLAG) == TIM_FLAG_Trigger) || \
963  ((FLAG) == TIM_FLAG_Break) || \
964  ((FLAG) == TIM_FLAG_CC1OF) || \
965  ((FLAG) == TIM_FLAG_CC2OF) || \
966  ((FLAG) == TIM_FLAG_CC3OF) || \
967  ((FLAG) == TIM_FLAG_CC4OF))
968 
969 
970 #define IS_TIM_CLEAR_FLAG(TIM_FLAG) ((((TIM_FLAG) & (uint16_t)0xE100) == 0x0000) && ((TIM_FLAG) != 0x0000))
971 
980 #define IS_TIM_IC_FILTER(ICFILTER) ((ICFILTER) <= 0xF)
981 
989 #define IS_TIM_EXT_FILTER(EXTFILTER) ((EXTFILTER) <= 0xF)
990 
997 #define TIM_OCReferenceClear_ETRF ((uint16_t)0x0008)
998 #define TIM_OCReferenceClear_OCREFCLR ((uint16_t)0x0000)
999 #define TIM_OCREFERENCECECLEAR_SOURCE(SOURCE) (((SOURCE) == TIM_OCReferenceClear_ETRF) || \
1000  ((SOURCE) == TIM_OCReferenceClear_OCREFCLR))
1001 
1008 #define TIM14_GPIO ((uint16_t)0x0000)
1009 #define TIM14_RTC_CLK ((uint16_t)0x0001)
1010 #define TIM14_HSEDiv32 ((uint16_t)0x0002)
1011 #define TIM14_MCO ((uint16_t)0x0003)
1012 
1013 #define IS_TIM_REMAP(TIM_REMAP) (((TIM_REMAP) == TIM14_GPIO)|| \
1014  ((TIM_REMAP) == TIM14_RTC_CLK) || \
1015  ((TIM_REMAP) == TIM14_HSEDiv32) || \
1016  ((TIM_REMAP) == TIM14_MCO))
1017 
1025 #define TIM_DMABurstLength_1Byte TIM_DMABurstLength_1Transfer
1026 #define TIM_DMABurstLength_2Bytes TIM_DMABurstLength_2Transfers
1027 #define TIM_DMABurstLength_3Bytes TIM_DMABurstLength_3Transfers
1028 #define TIM_DMABurstLength_4Bytes TIM_DMABurstLength_4Transfers
1029 #define TIM_DMABurstLength_5Bytes TIM_DMABurstLength_5Transfers
1030 #define TIM_DMABurstLength_6Bytes TIM_DMABurstLength_6Transfers
1031 #define TIM_DMABurstLength_7Bytes TIM_DMABurstLength_7Transfers
1032 #define TIM_DMABurstLength_8Bytes TIM_DMABurstLength_8Transfers
1033 #define TIM_DMABurstLength_9Bytes TIM_DMABurstLength_9Transfers
1034 #define TIM_DMABurstLength_10Bytes TIM_DMABurstLength_10Transfers
1035 #define TIM_DMABurstLength_11Bytes TIM_DMABurstLength_11Transfers
1036 #define TIM_DMABurstLength_12Bytes TIM_DMABurstLength_12Transfers
1037 #define TIM_DMABurstLength_13Bytes TIM_DMABurstLength_13Transfers
1038 #define TIM_DMABurstLength_14Bytes TIM_DMABurstLength_14Transfers
1039 #define TIM_DMABurstLength_15Bytes TIM_DMABurstLength_15Transfers
1040 #define TIM_DMABurstLength_16Bytes TIM_DMABurstLength_16Transfers
1041 #define TIM_DMABurstLength_17Bytes TIM_DMABurstLength_17Transfers
1042 #define TIM_DMABurstLength_18Bytes TIM_DMABurstLength_18Transfers
1043 
1051 /* Exported macro ------------------------------------------------------------*/
1052 /* Exported functions ------------------------------------------------------- */
1053 
1054 /* TimeBase management ********************************************************/
1055 void TIM_DeInit(TIM_TypeDef* TIMx);
1056 void TIM_TimeBaseInit(TIM_TypeDef* TIMx, TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1057 void TIM_TimeBaseStructInit(TIM_TimeBaseInitTypeDef* TIM_TimeBaseInitStruct);
1058 void TIM_PrescalerConfig(TIM_TypeDef* TIMx, uint16_t Prescaler, uint16_t TIM_PSCReloadMode);
1059 void TIM_CounterModeConfig(TIM_TypeDef* TIMx, uint16_t TIM_CounterMode);
1060 void TIM_SetCounter(TIM_TypeDef* TIMx, uint32_t Counter);
1061 void TIM_SetAutoreload(TIM_TypeDef* TIMx, uint32_t Autoreload);
1062 uint32_t TIM_GetCounter(TIM_TypeDef* TIMx);
1063 uint16_t TIM_GetPrescaler(TIM_TypeDef* TIMx);
1064 void TIM_UpdateDisableConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1065 void TIM_UpdateRequestConfig(TIM_TypeDef* TIMx, uint16_t TIM_UpdateSource);
1066 void TIM_ARRPreloadConfig(TIM_TypeDef* TIMx, FunctionalState NewState);
1067 void TIM_SelectOnePulseMode(TIM_TypeDef* TIMx, uint16_t TIM_OPMode);
1068 void TIM_SetClockDivision(TIM_TypeDef* TIMx, uint16_t TIM_CKD);
1069 void TIM_Cmd(TIM_TypeDef* TIMx, FunctionalState NewState);
1070 
1071 /* Advanced-control timers (TIM1) specific features*******************/
1072 void TIM_BDTRConfig(TIM_TypeDef* TIMx, TIM_BDTRInitTypeDef *TIM_BDTRInitStruct);
1073 void TIM_BDTRStructInit(TIM_BDTRInitTypeDef* TIM_BDTRInitStruct);
1074 void TIM_CtrlPWMOutputs(TIM_TypeDef* TIMx, FunctionalState NewState);
1075 
1076 /* Output Compare management **************************************************/
1077 void TIM_OC1Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1078 void TIM_OC2Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1079 void TIM_OC3Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1080 void TIM_OC4Init(TIM_TypeDef* TIMx, TIM_OCInitTypeDef* TIM_OCInitStruct);
1081 void TIM_OCStructInit(TIM_OCInitTypeDef* TIM_OCInitStruct);
1082 void TIM_SelectOCxM(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_OCMode);
1083 void TIM_SetCompare1(TIM_TypeDef* TIMx, uint32_t Compare1);
1084 void TIM_SetCompare2(TIM_TypeDef* TIMx, uint32_t Compare2);
1085 void TIM_SetCompare3(TIM_TypeDef* TIMx, uint32_t Compare3);
1086 void TIM_SetCompare4(TIM_TypeDef* TIMx, uint32_t Compare4);
1087 void TIM_ForcedOC1Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1088 void TIM_ForcedOC2Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1089 void TIM_ForcedOC3Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1090 void TIM_ForcedOC4Config(TIM_TypeDef* TIMx, uint16_t TIM_ForcedAction);
1091 void TIM_CCPreloadControl(TIM_TypeDef* TIMx, FunctionalState NewState);
1092 void TIM_OC1PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1093 void TIM_OC2PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1094 void TIM_OC3PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1095 void TIM_OC4PreloadConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPreload);
1096 void TIM_OC1FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1097 void TIM_OC2FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1098 void TIM_OC3FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1099 void TIM_OC4FastConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCFast);
1100 void TIM_ClearOC1Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1101 void TIM_ClearOC2Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1102 void TIM_ClearOC3Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1103 void TIM_ClearOC4Ref(TIM_TypeDef* TIMx, uint16_t TIM_OCClear);
1104 void TIM_OC1PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1105 void TIM_OC1NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1106 void TIM_OC2PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1107 void TIM_OC2NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1108 void TIM_OC3PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1109 void TIM_OC3NPolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCNPolarity);
1110 void TIM_OC4PolarityConfig(TIM_TypeDef* TIMx, uint16_t TIM_OCPolarity);
1111 void TIM_SelectOCREFClear(TIM_TypeDef* TIMx, uint16_t TIM_OCReferenceClear);
1112 void TIM_CCxCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCx);
1113 void TIM_CCxNCmd(TIM_TypeDef* TIMx, uint16_t TIM_Channel, uint16_t TIM_CCxN);
1114 void TIM_SelectCOM(TIM_TypeDef* TIMx, FunctionalState NewState);
1115 
1116 /* Input Capture management ***************************************************/
1117 void TIM_ICInit(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1118 void TIM_ICStructInit(TIM_ICInitTypeDef* TIM_ICInitStruct);
1119 void TIM_PWMIConfig(TIM_TypeDef* TIMx, TIM_ICInitTypeDef* TIM_ICInitStruct);
1120 uint32_t TIM_GetCapture1(TIM_TypeDef* TIMx);
1121 uint32_t TIM_GetCapture2(TIM_TypeDef* TIMx);
1122 uint32_t TIM_GetCapture3(TIM_TypeDef* TIMx);
1123 uint32_t TIM_GetCapture4(TIM_TypeDef* TIMx);
1124 void TIM_SetIC1Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1125 void TIM_SetIC2Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1126 void TIM_SetIC3Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1127 void TIM_SetIC4Prescaler(TIM_TypeDef* TIMx, uint16_t TIM_ICPSC);
1128 
1129 /* Interrupts, DMA and flags management ***************************************/
1130 void TIM_ITConfig(TIM_TypeDef* TIMx, uint16_t TIM_IT, FunctionalState NewState);
1131 void TIM_GenerateEvent(TIM_TypeDef* TIMx, uint16_t TIM_EventSource);
1132 FlagStatus TIM_GetFlagStatus(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1133 void TIM_ClearFlag(TIM_TypeDef* TIMx, uint16_t TIM_FLAG);
1134 ITStatus TIM_GetITStatus(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1135 void TIM_ClearITPendingBit(TIM_TypeDef* TIMx, uint16_t TIM_IT);
1136 void TIM_DMAConfig(TIM_TypeDef* TIMx, uint16_t TIM_DMABase, uint16_t TIM_DMABurstLength);
1137 void TIM_DMACmd(TIM_TypeDef* TIMx, uint16_t TIM_DMASource, FunctionalState NewState);
1138 void TIM_SelectCCDMA(TIM_TypeDef* TIMx, FunctionalState NewState);
1139 
1140 /* Clocks management **********************************************************/
1141 void TIM_InternalClockConfig(TIM_TypeDef* TIMx);
1142 void TIM_ITRxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1143 void TIM_TIxExternalClockConfig(TIM_TypeDef* TIMx, uint16_t TIM_TIxExternalCLKSource,
1144  uint16_t TIM_ICPolarity, uint16_t ICFilter);
1145 void TIM_ETRClockMode1Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1146  uint16_t ExtTRGFilter);
1147 void TIM_ETRClockMode2Config(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler,
1148  uint16_t TIM_ExtTRGPolarity, uint16_t ExtTRGFilter);
1149 
1150 
1151 /* Synchronization management *************************************************/
1152 void TIM_SelectInputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_InputTriggerSource);
1153 void TIM_SelectOutputTrigger(TIM_TypeDef* TIMx, uint16_t TIM_TRGOSource);
1154 void TIM_SelectSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_SlaveMode);
1155 void TIM_SelectMasterSlaveMode(TIM_TypeDef* TIMx, uint16_t TIM_MasterSlaveMode);
1156 void TIM_ETRConfig(TIM_TypeDef* TIMx, uint16_t TIM_ExtTRGPrescaler, uint16_t TIM_ExtTRGPolarity,
1157  uint16_t ExtTRGFilter);
1158 
1159 /* Specific interface management **********************************************/
1160 void TIM_EncoderInterfaceConfig(TIM_TypeDef* TIMx, uint16_t TIM_EncoderMode,
1161  uint16_t TIM_IC1Polarity, uint16_t TIM_IC2Polarity);
1162 void TIM_SelectHallSensor(TIM_TypeDef* TIMx, FunctionalState NewState);
1163 
1164 /* Specific remapping management **********************************************/
1165 void TIM_RemapConfig(TIM_TypeDef* TIMx, uint16_t TIM_Remap);
1166 
1167 
1168 #ifdef __cplusplus
1169 }
1170 #endif
1171 
1172 #endif /*__STM32F0XX_TIM_H */
1173 
1182 /************************ (C) COPYRIGHT STMicroelectronics *****END OF FILE****/