30 #ifndef __STM32F0XX_RCC_H
31 #define __STM32F0XX_RCC_H
38 #include "stm32f0xx.h"
52 uint32_t SYSCLK_Frequency;
53 uint32_t HCLK_Frequency;
54 uint32_t PCLK_Frequency;
55 uint32_t ADCCLK_Frequency;
56 uint32_t CECCLK_Frequency;
57 uint32_t I2C1CLK_Frequency;
58 uint32_t USART1CLK_Frequency;
71 #define RCC_HSE_OFF ((uint8_t)0x00)
72 #define RCC_HSE_ON ((uint8_t)0x01)
73 #define RCC_HSE_Bypass ((uint8_t)0x05)
74 #define IS_RCC_HSE(HSE) (((HSE) == RCC_HSE_OFF) || ((HSE) == RCC_HSE_ON) || \
75 ((HSE) == RCC_HSE_Bypass))
85 #define RCC_PLLSource_HSI_Div2 RCC_CFGR_PLLSRC_HSI_Div2
86 #define RCC_PLLSource_PREDIV1 RCC_CFGR_PLLSRC_PREDIV1
88 #define IS_RCC_PLL_SOURCE(SOURCE) (((SOURCE) == RCC_PLLSource_HSI_Div2) || \
89 ((SOURCE) == RCC_PLLSource_PREDIV1))
98 #define RCC_PLLMul_2 RCC_CFGR_PLLMULL2
99 #define RCC_PLLMul_3 RCC_CFGR_PLLMULL3
100 #define RCC_PLLMul_4 RCC_CFGR_PLLMULL4
101 #define RCC_PLLMul_5 RCC_CFGR_PLLMULL5
102 #define RCC_PLLMul_6 RCC_CFGR_PLLMULL6
103 #define RCC_PLLMul_7 RCC_CFGR_PLLMULL7
104 #define RCC_PLLMul_8 RCC_CFGR_PLLMULL8
105 #define RCC_PLLMul_9 RCC_CFGR_PLLMULL9
106 #define RCC_PLLMul_10 RCC_CFGR_PLLMULL10
107 #define RCC_PLLMul_11 RCC_CFGR_PLLMULL11
108 #define RCC_PLLMul_12 RCC_CFGR_PLLMULL12
109 #define RCC_PLLMul_13 RCC_CFGR_PLLMULL13
110 #define RCC_PLLMul_14 RCC_CFGR_PLLMULL14
111 #define RCC_PLLMul_15 RCC_CFGR_PLLMULL15
112 #define RCC_PLLMul_16 RCC_CFGR_PLLMULL16
113 #define IS_RCC_PLL_MUL(MUL) (((MUL) == RCC_PLLMul_2) || ((MUL) == RCC_PLLMul_3) || \
114 ((MUL) == RCC_PLLMul_4) || ((MUL) == RCC_PLLMul_5) || \
115 ((MUL) == RCC_PLLMul_6) || ((MUL) == RCC_PLLMul_7) || \
116 ((MUL) == RCC_PLLMul_8) || ((MUL) == RCC_PLLMul_9) || \
117 ((MUL) == RCC_PLLMul_10) || ((MUL) == RCC_PLLMul_11) || \
118 ((MUL) == RCC_PLLMul_12) || ((MUL) == RCC_PLLMul_13) || \
119 ((MUL) == RCC_PLLMul_14) || ((MUL) == RCC_PLLMul_15) || \
120 ((MUL) == RCC_PLLMul_16))
128 #define RCC_PREDIV1_Div1 RCC_CFGR2_PREDIV1_DIV1
129 #define RCC_PREDIV1_Div2 RCC_CFGR2_PREDIV1_DIV2
130 #define RCC_PREDIV1_Div3 RCC_CFGR2_PREDIV1_DIV3
131 #define RCC_PREDIV1_Div4 RCC_CFGR2_PREDIV1_DIV4
132 #define RCC_PREDIV1_Div5 RCC_CFGR2_PREDIV1_DIV5
133 #define RCC_PREDIV1_Div6 RCC_CFGR2_PREDIV1_DIV6
134 #define RCC_PREDIV1_Div7 RCC_CFGR2_PREDIV1_DIV7
135 #define RCC_PREDIV1_Div8 RCC_CFGR2_PREDIV1_DIV8
136 #define RCC_PREDIV1_Div9 RCC_CFGR2_PREDIV1_DIV9
137 #define RCC_PREDIV1_Div10 RCC_CFGR2_PREDIV1_DIV10
138 #define RCC_PREDIV1_Div11 RCC_CFGR2_PREDIV1_DIV11
139 #define RCC_PREDIV1_Div12 RCC_CFGR2_PREDIV1_DIV12
140 #define RCC_PREDIV1_Div13 RCC_CFGR2_PREDIV1_DIV13
141 #define RCC_PREDIV1_Div14 RCC_CFGR2_PREDIV1_DIV14
142 #define RCC_PREDIV1_Div15 RCC_CFGR2_PREDIV1_DIV15
143 #define RCC_PREDIV1_Div16 RCC_CFGR2_PREDIV1_DIV16
145 #define IS_RCC_PREDIV1(PREDIV1) (((PREDIV1) == RCC_PREDIV1_Div1) || ((PREDIV1) == RCC_PREDIV1_Div2) || \
146 ((PREDIV1) == RCC_PREDIV1_Div3) || ((PREDIV1) == RCC_PREDIV1_Div4) || \
147 ((PREDIV1) == RCC_PREDIV1_Div5) || ((PREDIV1) == RCC_PREDIV1_Div6) || \
148 ((PREDIV1) == RCC_PREDIV1_Div7) || ((PREDIV1) == RCC_PREDIV1_Div8) || \
149 ((PREDIV1) == RCC_PREDIV1_Div9) || ((PREDIV1) == RCC_PREDIV1_Div10) || \
150 ((PREDIV1) == RCC_PREDIV1_Div11) || ((PREDIV1) == RCC_PREDIV1_Div12) || \
151 ((PREDIV1) == RCC_PREDIV1_Div13) || ((PREDIV1) == RCC_PREDIV1_Div14) || \
152 ((PREDIV1) == RCC_PREDIV1_Div15) || ((PREDIV1) == RCC_PREDIV1_Div16))
161 #define RCC_SYSCLKSource_HSI RCC_CFGR_SW_HSI
162 #define RCC_SYSCLKSource_HSE RCC_CFGR_SW_HSE
163 #define RCC_SYSCLKSource_PLLCLK RCC_CFGR_SW_PLL
164 #define IS_RCC_SYSCLK_SOURCE(SOURCE) (((SOURCE) == RCC_SYSCLKSource_HSI) || \
165 ((SOURCE) == RCC_SYSCLKSource_HSE) || \
166 ((SOURCE) == RCC_SYSCLKSource_PLLCLK))
175 #define RCC_SYSCLK_Div1 RCC_CFGR_HPRE_DIV1
176 #define RCC_SYSCLK_Div2 RCC_CFGR_HPRE_DIV2
177 #define RCC_SYSCLK_Div4 RCC_CFGR_HPRE_DIV4
178 #define RCC_SYSCLK_Div8 RCC_CFGR_HPRE_DIV8
179 #define RCC_SYSCLK_Div16 RCC_CFGR_HPRE_DIV16
180 #define RCC_SYSCLK_Div64 RCC_CFGR_HPRE_DIV64
181 #define RCC_SYSCLK_Div128 RCC_CFGR_HPRE_DIV128
182 #define RCC_SYSCLK_Div256 RCC_CFGR_HPRE_DIV256
183 #define RCC_SYSCLK_Div512 RCC_CFGR_HPRE_DIV512
184 #define IS_RCC_HCLK(HCLK) (((HCLK) == RCC_SYSCLK_Div1) || ((HCLK) == RCC_SYSCLK_Div2) || \
185 ((HCLK) == RCC_SYSCLK_Div4) || ((HCLK) == RCC_SYSCLK_Div8) || \
186 ((HCLK) == RCC_SYSCLK_Div16) || ((HCLK) == RCC_SYSCLK_Div64) || \
187 ((HCLK) == RCC_SYSCLK_Div128) || ((HCLK) == RCC_SYSCLK_Div256) || \
188 ((HCLK) == RCC_SYSCLK_Div512))
197 #define RCC_HCLK_Div1 RCC_CFGR_PPRE_DIV1
198 #define RCC_HCLK_Div2 RCC_CFGR_PPRE_DIV2
199 #define RCC_HCLK_Div4 RCC_CFGR_PPRE_DIV4
200 #define RCC_HCLK_Div8 RCC_CFGR_PPRE_DIV8
201 #define RCC_HCLK_Div16 RCC_CFGR_PPRE_DIV16
202 #define IS_RCC_PCLK(PCLK) (((PCLK) == RCC_HCLK_Div1) || ((PCLK) == RCC_HCLK_Div2) || \
203 ((PCLK) == RCC_HCLK_Div4) || ((PCLK) == RCC_HCLK_Div8) || \
204 ((PCLK) == RCC_HCLK_Div16))
213 #define RCC_ADCCLK_HSI14 ((uint32_t)0x00000000)
214 #define RCC_ADCCLK_PCLK_Div2 ((uint32_t)0x01000000)
215 #define RCC_ADCCLK_PCLK_Div4 ((uint32_t)0x01004000)
217 #define IS_RCC_ADCCLK(ADCCLK) (((ADCCLK) == RCC_ADCCLK_HSI14) || ((ADCCLK) == RCC_ADCCLK_PCLK_Div2) || \
218 ((ADCCLK) == RCC_ADCCLK_PCLK_Div4))
228 #define RCC_CECCLK_HSI_Div244 ((uint32_t)0x00000000)
229 #define RCC_CECCLK_LSE RCC_CFGR3_CECSW
231 #define IS_RCC_CECCLK(CECCLK) (((CECCLK) == RCC_CECCLK_HSI_Div244) || ((CECCLK) == RCC_CECCLK_LSE))
241 #define RCC_I2C1CLK_HSI ((uint32_t)0x00000000)
242 #define RCC_I2C1CLK_SYSCLK RCC_CFGR3_I2C1SW
244 #define IS_RCC_I2CCLK(I2CCLK) (((I2CCLK) == RCC_I2C1CLK_HSI) || ((I2CCLK) == RCC_I2C1CLK_SYSCLK))
254 #define RCC_USART1CLK_PCLK ((uint32_t)0x00000000)
255 #define RCC_USART1CLK_SYSCLK RCC_CFGR3_USART1SW_0
256 #define RCC_USART1CLK_LSE RCC_CFGR3_USART1SW_1
257 #define RCC_USART1CLK_HSI RCC_CFGR3_USART1SW
259 #define IS_RCC_USARTCLK(USARTCLK) (((USARTCLK) == RCC_USART1CLK_PCLK) || ((USARTCLK) == RCC_USART1CLK_SYSCLK) || \
260 ((USARTCLK) == RCC_USART1CLK_LSE) || ((USARTCLK) == RCC_USART1CLK_HSI))
270 #define RCC_IT_LSIRDY ((uint8_t)0x01)
271 #define RCC_IT_LSERDY ((uint8_t)0x02)
272 #define RCC_IT_HSIRDY ((uint8_t)0x04)
273 #define RCC_IT_HSERDY ((uint8_t)0x08)
274 #define RCC_IT_PLLRDY ((uint8_t)0x10)
275 #define RCC_IT_HSI14RDY ((uint8_t)0x20)
276 #define RCC_IT_CSS ((uint8_t)0x80)
278 #define IS_RCC_IT(IT) ((((IT) & (uint8_t)0xC0) == 0x00) && ((IT) != 0x00))
280 #define IS_RCC_GET_IT(IT) (((IT) == RCC_IT_LSIRDY) || ((IT) == RCC_IT_LSERDY) || \
281 ((IT) == RCC_IT_HSIRDY) || ((IT) == RCC_IT_HSERDY) || \
282 ((IT) == RCC_IT_PLLRDY) || ((IT) == RCC_IT_HSI14RDY) || \
283 ((IT) == RCC_IT_CSS))
285 #define IS_RCC_CLEAR_IT(IT) ((((IT) & (uint8_t)0x40) == 0x00) && ((IT) != 0x00))
295 #define RCC_LSE_OFF ((uint32_t)0x00000000)
296 #define RCC_LSE_ON RCC_BDCR_LSEON
297 #define RCC_LSE_Bypass ((uint32_t)(RCC_BDCR_LSEON | RCC_BDCR_LSEBYP))
298 #define IS_RCC_LSE(LSE) (((LSE) == RCC_LSE_OFF) || ((LSE) == RCC_LSE_ON) || \
299 ((LSE) == RCC_LSE_Bypass))
308 #define RCC_RTCCLKSource_LSE RCC_BDCR_RTCSEL_LSE
309 #define RCC_RTCCLKSource_LSI RCC_BDCR_RTCSEL_LSI
310 #define RCC_RTCCLKSource_HSE_Div32 RCC_BDCR_RTCSEL_HSE
312 #define IS_RCC_RTCCLK_SOURCE(SOURCE) (((SOURCE) == RCC_RTCCLKSource_LSE) || \
313 ((SOURCE) == RCC_RTCCLKSource_LSI) || \
314 ((SOURCE) == RCC_RTCCLKSource_HSE_Div32))
323 #define RCC_LSEDrive_Low ((uint32_t)0x00000000)
324 #define RCC_LSEDrive_MediumLow RCC_BDCR_LSEDRV_0
325 #define RCC_LSEDrive_MediumHigh RCC_BDCR_LSEDRV_1
326 #define RCC_LSEDrive_High RCC_BDCR_LSEDRV
327 #define IS_RCC_LSE_DRIVE(DRIVE) (((DRIVE) == RCC_LSEDrive_Low) || ((DRIVE) == RCC_LSEDrive_MediumLow) || \
328 ((DRIVE) == RCC_LSEDrive_MediumHigh) || ((DRIVE) == RCC_LSEDrive_High))
337 #define RCC_AHBPeriph_GPIOA RCC_AHBENR_GPIOAEN
338 #define RCC_AHBPeriph_GPIOB RCC_AHBENR_GPIOBEN
339 #define RCC_AHBPeriph_GPIOC RCC_AHBENR_GPIOCEN
340 #define RCC_AHBPeriph_GPIOD RCC_AHBENR_GPIODEN
341 #define RCC_AHBPeriph_GPIOF RCC_AHBENR_GPIOFEN
342 #define RCC_AHBPeriph_TS RCC_AHBENR_TSEN
343 #define RCC_AHBPeriph_CRC RCC_AHBENR_CRCEN
344 #define RCC_AHBPeriph_FLITF RCC_AHBENR_FLITFEN
345 #define RCC_AHBPeriph_SRAM RCC_AHBENR_SRAMEN
346 #define RCC_AHBPeriph_DMA1 RCC_AHBENR_DMA1EN
348 #define IS_RCC_AHB_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFAA) == 0x00) && ((PERIPH) != 0x00))
349 #define IS_RCC_AHB_RST_PERIPH(PERIPH) ((((PERIPH) & 0xFEA1FFFF) == 0x00) && ((PERIPH) != 0x00))
359 #define RCC_APB2Periph_SYSCFG RCC_APB2ENR_SYSCFGEN
360 #define RCC_APB2Periph_ADC1 RCC_APB2ENR_ADC1EN
361 #define RCC_APB2Periph_TIM1 RCC_APB2ENR_TIM1EN
362 #define RCC_APB2Periph_SPI1 RCC_APB2ENR_SPI1EN
363 #define RCC_APB2Periph_USART1 RCC_APB2ENR_USART1EN
364 #define RCC_APB2Periph_TIM15 RCC_APB2ENR_TIM15EN
365 #define RCC_APB2Periph_TIM16 RCC_APB2ENR_TIM16EN
366 #define RCC_APB2Periph_TIM17 RCC_APB2ENR_TIM17EN
367 #define RCC_APB2Periph_DBGMCU RCC_APB2ENR_DBGMCUEN
369 #define IS_RCC_APB2_PERIPH(PERIPH) ((((PERIPH) & 0xFFB8A5FE) == 0x00) && ((PERIPH) != 0x00))
379 #define RCC_APB1Periph_TIM2 RCC_APB1ENR_TIM2EN
380 #define RCC_APB1Periph_TIM3 RCC_APB1ENR_TIM3EN
381 #define RCC_APB1Periph_TIM6 RCC_APB1ENR_TIM6EN
382 #define RCC_APB1Periph_TIM14 RCC_APB1ENR_TIM14EN
383 #define RCC_APB1Periph_WWDG RCC_APB1ENR_WWDGEN
384 #define RCC_APB1Periph_SPI2 RCC_APB1ENR_SPI2EN
385 #define RCC_APB1Periph_USART2 RCC_APB1ENR_USART2EN
386 #define RCC_APB1Periph_I2C1 RCC_APB1ENR_I2C1EN
387 #define RCC_APB1Periph_I2C2 RCC_APB1ENR_I2C2EN
388 #define RCC_APB1Periph_PWR RCC_APB1ENR_PWREN
389 #define RCC_APB1Periph_DAC RCC_APB1ENR_DACEN
390 #define RCC_APB1Periph_CEC RCC_APB1ENR_CECEN
392 #define IS_RCC_APB1_PERIPH(PERIPH) ((((PERIPH) & 0x8F9DB6EC) == 0x00) && ((PERIPH) != 0x00))
401 #define RCC_MCOSource_NoClock ((uint8_t)0x00)
402 #define RCC_MCOSource_HSI14 ((uint8_t)0x01)
403 #define RCC_MCOSource_LSI ((uint8_t)0x02)
404 #define RCC_MCOSource_LSE ((uint8_t)0x03)
405 #define RCC_MCOSource_SYSCLK ((uint8_t)0x04)
406 #define RCC_MCOSource_HSI ((uint8_t)0x05)
407 #define RCC_MCOSource_HSE ((uint8_t)0x06)
408 #define RCC_MCOSource_PLLCLK_Div2 ((uint8_t)0x07)
410 #define IS_RCC_MCO_SOURCE(SOURCE) (((SOURCE) == RCC_MCOSource_NoClock) || ((SOURCE) == RCC_MCOSource_HSI14) || \
411 ((SOURCE) == RCC_MCOSource_SYSCLK) || ((SOURCE) == RCC_MCOSource_HSI) || \
412 ((SOURCE) == RCC_MCOSource_HSE) || ((SOURCE) == RCC_MCOSource_PLLCLK_Div2)|| \
413 ((SOURCE) == RCC_MCOSource_LSI) || ((SOURCE) == RCC_MCOSource_LSE))
421 #define RCC_FLAG_HSIRDY ((uint8_t)0x01)
422 #define RCC_FLAG_HSERDY ((uint8_t)0x11)
423 #define RCC_FLAG_PLLRDY ((uint8_t)0x19)
424 #define RCC_FLAG_LSERDY ((uint8_t)0x21)
425 #define RCC_FLAG_LSIRDY ((uint8_t)0x41)
426 #define RCC_FLAG_V18PWRRSTF ((uint8_t)0x57)
427 #define RCC_FLAG_OBLRST ((uint8_t)0x59)
428 #define RCC_FLAG_PINRST ((uint8_t)0x5A)
429 #define RCC_FLAG_PORRST ((uint8_t)0x5B)
430 #define RCC_FLAG_SFTRST ((uint8_t)0x5C)
431 #define RCC_FLAG_IWDGRST ((uint8_t)0x5D)
432 #define RCC_FLAG_WWDGRST ((uint8_t)0x5E)
433 #define RCC_FLAG_LPWRRST ((uint8_t)0x5F)
434 #define RCC_FLAG_HSI14RDY ((uint8_t)0x61)
436 #define IS_RCC_FLAG(FLAG) (((FLAG) == RCC_FLAG_HSIRDY) || ((FLAG) == RCC_FLAG_HSERDY) || \
437 ((FLAG) == RCC_FLAG_PLLRDY) || ((FLAG) == RCC_FLAG_LSERDY) || \
438 ((FLAG) == RCC_FLAG_LSIRDY) || ((FLAG) == RCC_FLAG_OBLRST) || \
439 ((FLAG) == RCC_FLAG_PINRST) || ((FLAG) == RCC_FLAG_PORRST) || \
440 ((FLAG) == RCC_FLAG_SFTRST) || ((FLAG) == RCC_FLAG_IWDGRST)|| \
441 ((FLAG) == RCC_FLAG_WWDGRST) || ((FLAG) == RCC_FLAG_LPWRRST)|| \
442 ((FLAG) == RCC_FLAG_HSI14RDY)|| ((FLAG) == RCC_FLAG_V18PWRRSTF))
444 #define IS_RCC_HSI_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
445 #define IS_RCC_HSI14_CALIBRATION_VALUE(VALUE) ((VALUE) <= 0x1F)
472 void RCC_PLLConfig(uint32_t RCC_PLLSource, uint32_t RCC_PLLMul);
503 void RCC_ITConfig(uint8_t RCC_IT, FunctionalState NewState);