30 #ifndef __STM32F0XX_DMA_H
31 #define __STM32F0XX_DMA_H
38 #include "stm32f0xx.h"
61 uint32_t DMA_BufferSize;
65 uint32_t DMA_PeripheralInc;
68 uint32_t DMA_MemoryInc;
71 uint32_t DMA_PeripheralDataSize;
74 uint32_t DMA_MemoryDataSize;
82 uint32_t DMA_Priority;
95 #define IS_DMA_ALL_PERIPH(PERIPH) (((PERIPH) == DMA1_Channel1) || \
96 ((PERIPH) == DMA1_Channel2) || \
97 ((PERIPH) == DMA1_Channel3) || \
98 ((PERIPH) == DMA1_Channel4) || \
99 ((PERIPH) == DMA1_Channel5))
105 #define DMA_DIR_PeripheralSRC ((uint32_t)0x00000000)
106 #define DMA_DIR_PeripheralDST DMA_CCR_DIR
108 #define IS_DMA_DIR(DIR) (((DIR) == DMA_DIR_PeripheralSRC) || \
109 ((DIR) == DMA_DIR_PeripheralDST))
118 #define DMA_PeripheralInc_Disable ((uint32_t)0x00000000)
119 #define DMA_PeripheralInc_Enable DMA_CCR_PINC
121 #define IS_DMA_PERIPHERAL_INC_STATE(STATE) (((STATE) == DMA_PeripheralInc_Disable) || \
122 ((STATE) == DMA_PeripheralInc_Enable))
131 #define DMA_MemoryInc_Disable ((uint32_t)0x00000000)
132 #define DMA_MemoryInc_Enable DMA_CCR_MINC
134 #define IS_DMA_MEMORY_INC_STATE(STATE) (((STATE) == DMA_MemoryInc_Disable) || \
135 ((STATE) == DMA_MemoryInc_Enable))
144 #define DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000)
145 #define DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0
146 #define DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1
148 #define IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) (((SIZE) == DMA_PeripheralDataSize_Byte) || \
149 ((SIZE) == DMA_PeripheralDataSize_HalfWord) || \
150 ((SIZE) == DMA_PeripheralDataSize_Word))
159 #define DMA_MemoryDataSize_Byte ((uint32_t)0x00000000)
160 #define DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0
161 #define DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1
163 #define IS_DMA_MEMORY_DATA_SIZE(SIZE) (((SIZE) == DMA_MemoryDataSize_Byte) || \
164 ((SIZE) == DMA_MemoryDataSize_HalfWord) || \
165 ((SIZE) == DMA_MemoryDataSize_Word))
174 #define DMA_Mode_Normal ((uint32_t)0x00000000)
175 #define DMA_Mode_Circular DMA_CCR_CIRC
177 #define IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular))
186 #define DMA_Priority_VeryHigh DMA_CCR_PL
187 #define DMA_Priority_High DMA_CCR_PL_1
188 #define DMA_Priority_Medium DMA_CCR_PL_0
189 #define DMA_Priority_Low ((uint32_t)0x00000000)
191 #define IS_DMA_PRIORITY(PRIORITY) (((PRIORITY) == DMA_Priority_VeryHigh) || \
192 ((PRIORITY) == DMA_Priority_High) || \
193 ((PRIORITY) == DMA_Priority_Medium) || \
194 ((PRIORITY) == DMA_Priority_Low))
203 #define DMA_M2M_Disable ((uint32_t)0x00000000)
204 #define DMA_M2M_Enable DMA_CCR_MEM2MEM
206 #define IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable))
216 #define DMA_IT_TC DMA_CCR_TCIE
217 #define DMA_IT_HT DMA_CCR_HTIE
218 #define DMA_IT_TE DMA_CCR_TEIE
220 #define IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00))
222 #define DMA1_IT_GL1 DMA_ISR_GIF1
223 #define DMA1_IT_TC1 DMA_ISR_TCIF1
224 #define DMA1_IT_HT1 DMA_ISR_HTIF1
225 #define DMA1_IT_TE1 DMA_ISR_TEIF1
226 #define DMA1_IT_GL2 DMA_ISR_GIF2
227 #define DMA1_IT_TC2 DMA_ISR_TCIF2
228 #define DMA1_IT_HT2 DMA_ISR_HTIF2
229 #define DMA1_IT_TE2 DMA_ISR_TEIF2
230 #define DMA1_IT_GL3 DMA_ISR_GIF3
231 #define DMA1_IT_TC3 DMA_ISR_TCIF3
232 #define DMA1_IT_HT3 DMA_ISR_HTIF3
233 #define DMA1_IT_TE3 DMA_ISR_TEIF3
234 #define DMA1_IT_GL4 DMA_ISR_GIF4
235 #define DMA1_IT_TC4 DMA_ISR_TCIF4
236 #define DMA1_IT_HT4 DMA_ISR_HTIF4
237 #define DMA1_IT_TE4 DMA_ISR_TEIF4
238 #define DMA1_IT_GL5 DMA_ISR_GIF5
239 #define DMA1_IT_TC5 DMA_ISR_TCIF5
240 #define DMA1_IT_HT5 DMA_ISR_HTIF5
241 #define DMA1_IT_TE5 DMA_ISR_TEIF5
243 #define IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00))
245 #define IS_DMA_GET_IT(IT) (((IT) == DMA1_IT_GL1) || ((IT) == DMA1_IT_TC1) || \
246 ((IT) == DMA1_IT_HT1) || ((IT) == DMA1_IT_TE1) || \
247 ((IT) == DMA1_IT_GL2) || ((IT) == DMA1_IT_TC2) || \
248 ((IT) == DMA1_IT_HT2) || ((IT) == DMA1_IT_TE2) || \
249 ((IT) == DMA1_IT_GL3) || ((IT) == DMA1_IT_TC3) || \
250 ((IT) == DMA1_IT_HT3) || ((IT) == DMA1_IT_TE3) || \
251 ((IT) == DMA1_IT_GL4) || ((IT) == DMA1_IT_TC4) || \
252 ((IT) == DMA1_IT_HT4) || ((IT) == DMA1_IT_TE4) || \
253 ((IT) == DMA1_IT_GL5) || ((IT) == DMA1_IT_TC5) || \
254 ((IT) == DMA1_IT_HT5) || ((IT) == DMA1_IT_TE5))
263 #define DMA1_FLAG_GL1 DMA_ISR_GIF1
264 #define DMA1_FLAG_TC1 DMA_ISR_TCIF1
265 #define DMA1_FLAG_HT1 DMA_ISR_HTIF1
266 #define DMA1_FLAG_TE1 DMA_ISR_TEIF1
267 #define DMA1_FLAG_GL2 DMA_ISR_GIF2
268 #define DMA1_FLAG_TC2 DMA_ISR_TCIF2
269 #define DMA1_FLAG_HT2 DMA_ISR_HTIF2
270 #define DMA1_FLAG_TE2 DMA_ISR_TEIF2
271 #define DMA1_FLAG_GL3 DMA_ISR_GIF3
272 #define DMA1_FLAG_TC3 DMA_ISR_TCIF3
273 #define DMA1_FLAG_HT3 DMA_ISR_HTIF3
274 #define DMA1_FLAG_TE3 DMA_ISR_TEIF3
275 #define DMA1_FLAG_GL4 DMA_ISR_GIF4
276 #define DMA1_FLAG_TC4 DMA_ISR_TCIF4
277 #define DMA1_FLAG_HT4 DMA_ISR_HTIF4
278 #define DMA1_FLAG_TE4 DMA_ISR_TEIF4
279 #define DMA1_FLAG_GL5 DMA_ISR_GIF5
280 #define DMA1_FLAG_TC5 DMA_ISR_TCIF5
281 #define DMA1_FLAG_HT5 DMA_ISR_HTIF5
282 #define DMA1_FLAG_TE5 DMA_ISR_TEIF5
284 #define IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00))
286 #define IS_DMA_GET_FLAG(FLAG) (((FLAG) == DMA1_FLAG_GL1) || ((FLAG) == DMA1_FLAG_TC1) || \
287 ((FLAG) == DMA1_FLAG_HT1) || ((FLAG) == DMA1_FLAG_TE1) || \
288 ((FLAG) == DMA1_FLAG_GL2) || ((FLAG) == DMA1_FLAG_TC2) || \
289 ((FLAG) == DMA1_FLAG_HT2) || ((FLAG) == DMA1_FLAG_TE2) || \
290 ((FLAG) == DMA1_FLAG_GL3) || ((FLAG) == DMA1_FLAG_TC3) || \
291 ((FLAG) == DMA1_FLAG_HT3) || ((FLAG) == DMA1_FLAG_TE3) || \
292 ((FLAG) == DMA1_FLAG_GL4) || ((FLAG) == DMA1_FLAG_TC4) || \
293 ((FLAG) == DMA1_FLAG_HT4) || ((FLAG) == DMA1_FLAG_TE4) || \
294 ((FLAG) == DMA1_FLAG_GL5) || ((FLAG) == DMA1_FLAG_TC5) || \
295 ((FLAG) == DMA1_FLAG_HT5) || ((FLAG) == DMA1_FLAG_TE5))
305 #define IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000))
319 void DMA_DeInit(DMA_Channel_TypeDef* DMAy_Channelx);
324 void DMA_Cmd(DMA_Channel_TypeDef* DMAy_Channelx, FunctionalState NewState);
331 void DMA_ITConfig(DMA_Channel_TypeDef* DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState);