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#define | IS_DMA_ALL_PERIPH(PERIPH) |
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#define | DMA_DIR_PeripheralSRC ((uint32_t)0x00000000) |
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#define | DMA_DIR_PeripheralDST DMA_CCR_DIR |
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#define | IS_DMA_DIR(DIR) |
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#define | DMA_PeripheralInc_Disable ((uint32_t)0x00000000) |
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#define | DMA_PeripheralInc_Enable DMA_CCR_PINC |
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#define | IS_DMA_PERIPHERAL_INC_STATE(STATE) |
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#define | DMA_MemoryInc_Disable ((uint32_t)0x00000000) |
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#define | DMA_MemoryInc_Enable DMA_CCR_MINC |
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#define | IS_DMA_MEMORY_INC_STATE(STATE) |
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#define | DMA_PeripheralDataSize_Byte ((uint32_t)0x00000000) |
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#define | DMA_PeripheralDataSize_HalfWord DMA_CCR_PSIZE_0 |
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#define | DMA_PeripheralDataSize_Word DMA_CCR_PSIZE_1 |
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#define | IS_DMA_PERIPHERAL_DATA_SIZE(SIZE) |
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#define | DMA_MemoryDataSize_Byte ((uint32_t)0x00000000) |
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#define | DMA_MemoryDataSize_HalfWord DMA_CCR_MSIZE_0 |
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#define | DMA_MemoryDataSize_Word DMA_CCR_MSIZE_1 |
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#define | IS_DMA_MEMORY_DATA_SIZE(SIZE) |
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#define | DMA_Mode_Normal ((uint32_t)0x00000000) |
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#define | DMA_Mode_Circular DMA_CCR_CIRC |
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#define | IS_DMA_MODE(MODE) (((MODE) == DMA_Mode_Normal) || ((MODE) == DMA_Mode_Circular)) |
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#define | DMA_Priority_VeryHigh DMA_CCR_PL |
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#define | DMA_Priority_High DMA_CCR_PL_1 |
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#define | DMA_Priority_Medium DMA_CCR_PL_0 |
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#define | DMA_Priority_Low ((uint32_t)0x00000000) |
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#define | IS_DMA_PRIORITY(PRIORITY) |
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#define | DMA_M2M_Disable ((uint32_t)0x00000000) |
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#define | DMA_M2M_Enable DMA_CCR_MEM2MEM |
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#define | IS_DMA_M2M_STATE(STATE) (((STATE) == DMA_M2M_Disable) || ((STATE) == DMA_M2M_Enable)) |
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#define | DMA_IT_TC DMA_CCR_TCIE |
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#define | DMA_IT_HT DMA_CCR_HTIE |
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#define | DMA_IT_TE DMA_CCR_TEIE |
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#define | IS_DMA_CONFIG_IT(IT) ((((IT) & 0xFFFFFFF1) == 0x00) && ((IT) != 0x00)) |
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#define | DMA1_IT_GL1 DMA_ISR_GIF1 |
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#define | DMA1_IT_TC1 DMA_ISR_TCIF1 |
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#define | DMA1_IT_HT1 DMA_ISR_HTIF1 |
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#define | DMA1_IT_TE1 DMA_ISR_TEIF1 |
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#define | DMA1_IT_GL2 DMA_ISR_GIF2 |
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#define | DMA1_IT_TC2 DMA_ISR_TCIF2 |
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#define | DMA1_IT_HT2 DMA_ISR_HTIF2 |
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#define | DMA1_IT_TE2 DMA_ISR_TEIF2 |
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#define | DMA1_IT_GL3 DMA_ISR_GIF3 |
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#define | DMA1_IT_TC3 DMA_ISR_TCIF3 |
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#define | DMA1_IT_HT3 DMA_ISR_HTIF3 |
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#define | DMA1_IT_TE3 DMA_ISR_TEIF3 |
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#define | DMA1_IT_GL4 DMA_ISR_GIF4 |
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#define | DMA1_IT_TC4 DMA_ISR_TCIF4 |
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#define | DMA1_IT_HT4 DMA_ISR_HTIF4 |
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#define | DMA1_IT_TE4 DMA_ISR_TEIF4 |
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#define | DMA1_IT_GL5 DMA_ISR_GIF5 |
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#define | DMA1_IT_TC5 DMA_ISR_TCIF5 |
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#define | DMA1_IT_HT5 DMA_ISR_HTIF5 |
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#define | DMA1_IT_TE5 DMA_ISR_TEIF5 |
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#define | IS_DMA_CLEAR_IT(IT) ((((IT) & 0xFFF00000) == 0x00) && ((IT) != 0x00)) |
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#define | IS_DMA_GET_IT(IT) |
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#define | DMA1_FLAG_GL1 DMA_ISR_GIF1 |
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#define | DMA1_FLAG_TC1 DMA_ISR_TCIF1 |
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#define | DMA1_FLAG_HT1 DMA_ISR_HTIF1 |
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#define | DMA1_FLAG_TE1 DMA_ISR_TEIF1 |
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#define | DMA1_FLAG_GL2 DMA_ISR_GIF2 |
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#define | DMA1_FLAG_TC2 DMA_ISR_TCIF2 |
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#define | DMA1_FLAG_HT2 DMA_ISR_HTIF2 |
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#define | DMA1_FLAG_TE2 DMA_ISR_TEIF2 |
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#define | DMA1_FLAG_GL3 DMA_ISR_GIF3 |
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#define | DMA1_FLAG_TC3 DMA_ISR_TCIF3 |
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#define | DMA1_FLAG_HT3 DMA_ISR_HTIF3 |
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#define | DMA1_FLAG_TE3 DMA_ISR_TEIF3 |
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#define | DMA1_FLAG_GL4 DMA_ISR_GIF4 |
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#define | DMA1_FLAG_TC4 DMA_ISR_TCIF4 |
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#define | DMA1_FLAG_HT4 DMA_ISR_HTIF4 |
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#define | DMA1_FLAG_TE4 DMA_ISR_TEIF4 |
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#define | DMA1_FLAG_GL5 DMA_ISR_GIF5 |
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#define | DMA1_FLAG_TC5 DMA_ISR_TCIF5 |
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#define | DMA1_FLAG_HT5 DMA_ISR_HTIF5 |
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#define | DMA1_FLAG_TE5 DMA_ISR_TEIF5 |
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#define | IS_DMA_CLEAR_FLAG(FLAG) ((((FLAG) & 0xFFF00000) == 0x00) && ((FLAG) != 0x00)) |
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#define | IS_DMA_GET_FLAG(FLAG) |
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#define | IS_DMA_BUFFER_SIZE(SIZE) (((SIZE) >= 0x1) && ((SIZE) < 0x10000)) |
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void | DMA_DeInit (DMA_Channel_TypeDef *DMAy_Channelx) |
| Deinitializes the DMAy Channelx registers to their default reset values. More...
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void | DMA_Init (DMA_Channel_TypeDef *DMAy_Channelx, DMA_InitTypeDef *DMA_InitStruct) |
| Initializes the DMAy Channelx according to the specified parameters in the DMA_InitStruct. More...
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void | DMA_StructInit (DMA_InitTypeDef *DMA_InitStruct) |
| Fills each DMA_InitStruct member with its default value. More...
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void | DMA_Cmd (DMA_Channel_TypeDef *DMAy_Channelx, FunctionalState NewState) |
| Enables or disables the specified DMAy Channelx. More...
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void | DMA_SetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx, uint16_t DataNumber) |
| Sets the number of data units in the current DMAy Channelx transfer. More...
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uint16_t | DMA_GetCurrDataCounter (DMA_Channel_TypeDef *DMAy_Channelx) |
| Returns the number of remaining data units in the current DMAy Channelx transfer. More...
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void | DMA_ITConfig (DMA_Channel_TypeDef *DMAy_Channelx, uint32_t DMA_IT, FunctionalState NewState) |
| Enables or disables the specified DMAy Channelx interrupts. More...
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FlagStatus | DMA_GetFlagStatus (uint32_t DMA_FLAG) |
| Checks whether the specified DMAy Channelx flag is set or not. More...
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void | DMA_ClearFlag (uint32_t DMA_FLAG) |
| Clears the DMAy Channelx's pending flags. More...
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ITStatus | DMA_GetITStatus (uint32_t DMA_IT) |
| Checks whether the specified DMAy Channelx interrupt has occurred or not. More...
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void | DMA_ClearITPendingBit (uint32_t DMA_IT) |
| Clears the DMAy Channelx's interrupt pending bits. More...
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This file contains all the functions prototypes for the DMA firmware library.
- Author
- MCD Application Team
- Version
- V1.0.1
- Date
- 20-April-2012
- Attention
© COPYRIGHT 2012 STMicroelectronics
Licensed under MCD-ST Liberty SW License Agreement V2, (the "License"); You may not use this file except in compliance with the License. You may obtain a copy of the License at:
http://www.st.com/software_license_agreement_liberty_v2
Unless required by applicable law or agreed to in writing, software distributed under the License is distributed on an "AS IS" BASIS, WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied. See the License for the specific language governing permissions and limitations under the License.