30 #ifndef ___STM32F0XX_I2C_CPAL_HAL_H
31 #define ___STM32F0XX_I2C_CPAL_HAL_H
39 #include "stm32f0xx.h"
40 #include "stm32f0xx_i2c.h"
41 #include "stm32f0xx_dma.h"
42 #include "stm32f0xx_gpio.h"
43 #include "stm32f0xx_rcc.h"
44 #include "stm32f0xx_misc.h"
116 #define CPAL_I2C1_SCL_GPIO_PORT GPIOB
117 #define CPAL_I2C1_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
118 #define CPAL_I2C1_SCL_GPIO_PIN GPIO_Pin_6
119 #define CPAL_I2C1_SCL_GPIO_PINSOURCE GPIO_PinSource6
121 #define CPAL_I2C1_SDA_GPIO_PORT GPIOB
122 #define CPAL_I2C1_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
123 #define CPAL_I2C1_SDA_GPIO_PIN GPIO_Pin_7
124 #define CPAL_I2C1_SDA_GPIO_PINSOURCE GPIO_PinSource7
128 #define CPAL_I2C2_SCL_GPIO_PORT GPIOB
129 #define CPAL_I2C2_SCL_GPIO_CLK RCC_AHBPeriph_GPIOB
130 #define CPAL_I2C2_SCL_GPIO_PIN GPIO_Pin_10
131 #define CPAL_I2C2_SCL_GPIO_PINSOURCE GPIO_PinSource10
133 #define CPAL_I2C2_SDA_GPIO_PORT GPIOB
134 #define CPAL_I2C2_SDA_GPIO_CLK RCC_AHBPeriph_GPIOB
135 #define CPAL_I2C2_SDA_GPIO_PIN GPIO_Pin_11
136 #define CPAL_I2C2_SDA_GPIO_PINSOURCE GPIO_PinSource11
167 #define CPAL_I2C1_DMA_TX_Channel DMA1_Channel2
168 #define CPAL_I2C1_DMA_RX_Channel DMA1_Channel3
171 #define CPAL_I2C2_DMA_TX_Channel DMA1_Channel4
172 #define CPAL_I2C2_DMA_RX_Channel DMA1_Channel5
193 #define I2C1_IT_PRIO I2C1_IT_OFFSET_PREPRIO + 2
194 #define I2C1_IT_DMA_PRIO I2C1_IT_OFFSET_PREPRIO + 0
197 #define I2C2_IT_PRIO I2C2_IT_OFFSET_PREPRIO + 2
198 #define I2C2_IT_DMA_PRIO I2C2_IT_OFFSET_PREPRIO + 0
215 #define CPAL_I2C_DEV_NUM 2
218 #define CPAL_DMA_CCR_EN DMA_CCR_EN
221 #define CPAL_OPT_DMA_IT_MASK ((uint32_t)0x00003F00)
224 #define CPAL_I2C_STATUS_ERR_MASK ((uint32_t)0x00000700)
227 #define CPAL_I2C_STATUS_EVT_MASK ((uint16_t)0x0000000FE)
230 #define CPAL_OPT_I2C_DMA_TX_IT_MASK ((uint32_t)0x00000700)
233 #define CPAL_OPT_I2C_DMA_RX_IT_MASK ((uint32_t)0x00003800)
236 #define CPAL_I2C_EVT_ADDR I2C_ISR_ADDR
237 #define CPAL_I2C_EVT_STOP I2C_ISR_STOPF
238 #define CPAL_I2C_EVT_NACK I2C_ISR_NACKF
239 #define CPAL_I2C_EVT_RXNE I2C_ISR_RXNE
240 #define CPAL_I2C_EVT_TXIS I2C_ISR_TXIS
241 #define CPAL_I2C_EVT_TCR I2C_ISR_TCR
242 #define CPAL_I2C_EVT_TC I2C_ISR_TC
246 #define CPAL_I2C1_CLK RCC_APB1Periph_I2C1
247 #define CPAL_I2C1_TXDR ((uint32_t)0x40005428)
248 #define CPAL_I2C1_RXDR ((uint32_t)0x40005424)
249 #define CPAL_I2C1_AF GPIO_AF_1
251 #define CPAL_I2C1_DMA DMA1
252 #define CPAL_I2C1_DMA_CLK RCC_AHBPeriph_DMA1
254 #define CPAL_I2C1_IT_IRQn I2C1_IRQn
255 #define CPAL_I2C1_DMA_IRQn DMA1_Channel2_3_IRQn
257 #define CPAL_I2C1_DMA_IRQHandler DMA1_Channel2_3_IRQHandler
259 #define CPAL_I2C1_DMA_TX_TC_FLAG DMA1_FLAG_TC2
260 #define CPAL_I2C1_DMA_TX_HT_FLAG DMA1_FLAG_HT2
261 #define CPAL_I2C1_DMA_TX_TE_FLAG DMA1_FLAG_TE2
263 #define CPAL_I2C1_DMA_RX_TC_FLAG DMA1_FLAG_TC3
264 #define CPAL_I2C1_DMA_RX_HT_FLAG DMA1_FLAG_HT3
265 #define CPAL_I2C1_DMA_RX_TE_FLAG DMA1_FLAG_TE3
269 #define CPAL_I2C2_CLK RCC_APB1Periph_I2C2
270 #define CPAL_I2C2_TXDR ((uint32_t)0x40005828)
271 #define CPAL_I2C2_RXDR ((uint32_t)0x40005824)
272 #define CPAL_I2C2_AF GPIO_AF_1
274 #define CPAL_I2C2_DMA DMA1
275 #define CPAL_I2C2_DMA_CLK RCC_AHBPeriph_DMA1
277 #define CPAL_I2C2_IT_IRQn I2C2_IRQn
278 #define CPAL_I2C2_DMA_IRQn DMA1_Channel4_5_IRQn
280 #define CPAL_I2C2_DMA_IRQHandler DMA1_Channel4_5_IRQHandler
282 #define CPAL_I2C2_DMA_TX_TC_FLAG DMA1_FLAG_TC4
283 #define CPAL_I2C2_DMA_TX_HT_FLAG DMA1_FLAG_HT4
284 #define CPAL_I2C2_DMA_TX_TE_FLAG DMA1_FLAG_TE4
286 #define CPAL_I2C2_DMA_RX_TC_FLAG DMA1_FLAG_TC5
287 #define CPAL_I2C2_DMA_RX_HT_FLAG DMA1_FLAG_HT5
288 #define CPAL_I2C2_DMA_RX_TE_FLAG DMA1_FLAG_TE5
295 #define __I2C_CLK_CMD(clk,cmd) RCC_APB1PeriphClockCmd((clk),(cmd))
297 #define __I2C_RCC_RESET(clk) RCC_APB1PeriphResetCmd((clk),ENABLE);\
298 RCC_APB1PeriphResetCmd((clk),DISABLE)
300 #define __I2C_GPIO_CLK_CMD(clk,cmd) RCC_AHBPeriphClockCmd((clk),(cmd))
302 #define __DMA_CLK_CMD(clk,cmd) RCC_AHBPeriphClockCmd((clk),(cmd))
304 #define __DMA_RESET_CMD(clk,cmd) RCC_AHBPeriphResetCmd((clk),(cmd))
311 #define __CPAL_I2C_HAL_ENABLE_DMATX(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= CPAL_DMA_CCR_EN
313 #define __CPAL_I2C_HAL_DISABLE_DMATX(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN
315 #define __CPAL_I2C_HAL_ENABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= CPAL_DMA_CCR_EN
317 #define __CPAL_I2C_HAL_DISABLE_DMARX(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR &= ~CPAL_DMA_CCR_EN
321 #define __I2C_HAL_ENABLE_DMATX_TCIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TC
323 #define __I2C_HAL_ENABLE_DMATX_HTIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_HT
325 #define __I2C_HAL_ENABLE_DMATX_TEIT(device) CPAL_I2C_DMA_TX_Channel[(device)]->CCR |= DMA_IT_TE
327 #define __I2C_HAL_ENABLE_DMARX_TCIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TC
329 #define __I2C_HAL_ENABLE_DMARX_HTIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_HT
331 #define __I2C_HAL_ENABLE_DMARX_TEIT(device) CPAL_I2C_DMA_RX_Channel[(device)]->CCR |= DMA_IT_TE
335 #define __CPAL_I2C_HAL_GET_DMATX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \
336 | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)]))
338 #define __CPAL_I2C_HAL_GET_DMATX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TC_FLAG [(device)])
340 #define __CPAL_I2C_HAL_GET_DMATX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_HT_FLAG [(device)])
342 #define __CPAL_I2C_HAL_GET_DMATX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_TX_TE_FLAG [(device)])
344 #define __CPAL_I2C_HAL_GET_DMARX_IT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \
345 | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)]))
347 #define __CPAL_I2C_HAL_GET_DMARX_TCIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TC_FLAG [(device)])
349 #define __CPAL_I2C_HAL_GET_DMARX_HTIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_HT_FLAG [(device)])
351 #define __CPAL_I2C_HAL_GET_DMARX_TEIT(device) (uint32_t)(CPAL_I2C_DMA[(device)]->ISR & CPAL_I2C_DMA_RX_TE_FLAG [(device)])
353 #define __CPAL_I2C_HAL_CLEAR_DMATX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_TX_TC_FLAG[(device)] \
354 | CPAL_I2C_DMA_TX_HT_FLAG[(device)] | CPAL_I2C_DMA_TX_TE_FLAG[(device)])
356 #define __CPAL_I2C_HAL_CLEAR_DMARX_IT(device) CPAL_I2C_DMA[(device)]->IFCR = (CPAL_I2C_DMA_RX_TC_FLAG[(device)] \
357 | CPAL_I2C_DMA_RX_HT_FLAG[(device)] | CPAL_I2C_DMA_RX_TE_FLAG[(device)])
361 #define __CPAL_I2C_HAL_DMATX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_TX_Channel[(device)]->CNDTR)
363 #define __CPAL_I2C_HAL_DMARX_GET_CNDT(device) (uint32_t)(CPAL_I2C_DMA_RX_Channel[(device)]->CNDTR)
370 #define __CPAL_I2C_HAL_ENABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_PE
372 #define __CPAL_I2C_HAL_DISABLE_DEV(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_PE
376 #define __CPAL_I2C_HAL_SWRST(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_SWRST; \
377 CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_SWRST
381 #define __CPAL_I2C_HAL_ENABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_WUPEN
383 #define __CPAL_I2C_HAL_DISABLE_WAKEUP(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_WUPEN
387 #define __CPAL_I2C_HAL_DISABLE_ALLIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TXIE | I2C_CR1_RXIE | I2C_CR1_ADDRIE | \
388 I2C_CR1_STOPIE | I2C_CR1_TCIE | I2C_CR1_ERRIE | I2C_CR1_NACKIE)
390 #define __CPAL_I2C_HAL_ENABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ERRIE | I2C_CR1_NACKIE)
392 #define __CPAL_I2C_HAL_DISABLE_ERRIT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ERRIE | I2C_CR1_NACKIE)
395 #define __CPAL_I2C_HAL_ENABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE)
397 #define __CPAL_I2C_HAL_DISABLE_MASTER_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_TCIE | I2C_CR1_STOPIE)
399 #define __CPAL_I2C_HAL_ENABLE_MASTER_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_TXIE)
401 #define __CPAL_I2C_HAL_ENABLE_MASTER_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_TCIE | I2C_CR1_STOPIE | I2C_CR1_RXIE)
404 #define __CPAL_I2C_HAL_ENABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE)
406 #define __CPAL_I2C_HAL_DISABLE_SLAVE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~(I2C_CR1_ADDRIE | I2C_CR1_STOPIE)
408 #define __CPAL_I2C_HAL_ENABLE_SLAVE_TXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_TXIE)
410 #define __CPAL_I2C_HAL_ENABLE_SLAVE_RXIT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= (I2C_CR1_ADDRIE | I2C_CR1_STOPIE | I2C_CR1_RXIE)
413 #define __CPAL_I2C_HAL_ENABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_STOPIE
415 #define __CPAL_I2C_HAL_DISABLE_STOPIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_STOPIE
417 #define __CPAL_I2C_HAL_ENABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_ADDRIE
419 #define __CPAL_I2C_HAL_DISABLE_ADDRIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_ADDRIE
421 #define __CPAL_I2C_HAL_ENABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TCIE
423 #define __CPAL_I2C_HAL_DISABLE_TCIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TCIE
425 #define __CPAL_I2C_HAL_ENABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXIE
427 #define __CPAL_I2C_HAL_DISABLE_TXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXIE
429 #define __CPAL_I2C_HAL_ENABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXIE
431 #define __CPAL_I2C_HAL_DISABLE_RXIE_IT(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXIE
436 #define __CPAL_I2C_HAL_SADD_CONF(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_SADD; \
437 CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((value) & 0x000003FF)
439 #define __CPAL_I2C_HAL_OA2_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2; \
440 CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) & 0x000000FE)
442 #define __CPAL_I2C_HAL_OA2_MASK_CONF(device,value) CPAL_I2C_DEVICE[(device)]->OAR2 &= ~I2C_OAR2_OA2MSK; \
443 CPAL_I2C_DEVICE[(device)]->OAR2 |= (uint32_t)((value) << 8)
445 #define __CPAL_I2C_HAL_ENABLE_OA2(device) CPAL_I2C_DEVICE[(device)]->OAR2 |= I2C_OAR2_OA2EN
447 #define __CPAL_I2C_HAL_ENABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_ADD10
449 #define __CPAL_I2C_HAL_DISABLE_ADD10(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_ADD10
451 #define __CPAL_I2C_HAL_ENABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_HEAD10R
453 #define __CPAL_I2C_HAL_DISABLE_COMPLETE_HEAD10R(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_HEAD10R
455 #define __CPAL_I2C_HAL_ENABLE_GENCALL(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_GCEN
457 #define __CPAL_I2C_HAL_REQ_WRITE_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RD_WRN
459 #define __CPAL_I2C_HAL_REQ_READ_TRANSFER(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RD_WRN
461 #define __CPAL_I2C_HAL_GET_OA1(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR1_OA1)
463 #define __CPAL_I2C_HAL_GET_OA2(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2)
465 #define __CPAL_I2C_HAL_GET_OA2_MASK(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_OAR2_OA2MSK) >> 8)
467 #define __CPAL_I2C_HAL_GET_ADDCODE(device) (uint32_t)((CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDCODE) >> 17)
469 #define __CPAL_I2C_HAL_GET_DIR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_DIR)
473 #define __CPAL_I2C_HAL_CR2_UPDATE(device,value) CPAL_I2C_DEVICE[(device)]->CR2 = value
475 #define __CPAL_I2C_HAL_ENABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_TXDMAEN
477 #define __CPAL_I2C_HAL_DISABLE_TXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_TXDMAEN
479 #define __CPAL_I2C_HAL_ENABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_RXDMAEN
481 #define __CPAL_I2C_HAL_DISABLE_RXDMAREQ(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_RXDMAEN
483 #define __CPAL_I2C_HAL_ENABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_NACK
485 #define __CPAL_I2C_HAL_DISABLE_NACK(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NACK
487 #define __CPAL_I2C_HAL_ENABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_AUTOEND
489 #define __CPAL_I2C_HAL_DISABLE_AUTOEND(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_AUTOEND
491 #define __CPAL_I2C_HAL_ENABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_RELOAD
493 #define __CPAL_I2C_HAL_DISABLE_RELOAD(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_RELOAD
495 #define __CPAL_I2C_HAL_ENABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 |= I2C_CR1_NOSTRETCH
497 #define __CPAL_I2C_HAL_DISABLE_NOSTRETCH(device) CPAL_I2C_DEVICE[(device)]->CR1 &= ~I2C_CR1_NOSTRETCH
499 #define __CPAL_I2C_HAL_START(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_START
501 #define __CPAL_I2C_HAL_STOP(device) CPAL_I2C_DEVICE[(device)]->CR2 |= I2C_CR2_STOP
505 #define __CPAL_I2C_HAL_RECEIVE(device) (uint8_t)(CPAL_I2C_DEVICE[(device)]->RXDR)
507 #define __CPAL_I2C_HAL_SEND(device,value) CPAL_I2C_DEVICE[(device)]->TXDR = (uint8_t)((value))
509 #define __CPAL_I2C_HAL_SET_NBYTES(device,value) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES; \
510 CPAL_I2C_DEVICE[(device)]->CR2 |= (uint32_t)((uint32_t)(value) << 16)
512 #define __CPAL_I2C_HAL_GET_NBYTES(device,value) (uint32_t)((CPAL_I2C_DEVICE[(device)]->CR2 & I2C_CR2_NBYTES) >> 16)
514 #define __CPAL_I2C_HAL_CLEAR_NBYTES(device) CPAL_I2C_DEVICE[(device)]->CR2 &= ~I2C_CR2_NBYTES
518 #define __CPAL_I2C_HAL_GET_EVENT(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_EVT_MASK)
520 #define __CPAL_I2C_HAL_GET_ERROR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & CPAL_I2C_STATUS_ERR_MASK)
522 #define __CPAL_I2C_HAL_GET_TXE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXE)
524 #define __CPAL_I2C_HAL_GET_TXIS(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TXIS)
526 #define __CPAL_I2C_HAL_GET_RXNE(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_RXNE)
528 #define __CPAL_I2C_HAL_GET_ADDR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ADDR)
530 #define __CPAL_I2C_HAL_GET_NACK(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_NACKF)
532 #define __CPAL_I2C_HAL_GET_STOP(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_STOPF)
534 #define __CPAL_I2C_HAL_GET_TC(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TC)
536 #define __CPAL_I2C_HAL_GET_TCR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_TCR)
538 #define __CPAL_I2C_HAL_GET_BERR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BERR)
540 #define __CPAL_I2C_HAL_GET_ARLO(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_ARLO)
542 #define __CPAL_I2C_HAL_GET_OVR(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_OVR)
544 #define __CPAL_I2C_HAL_GET_BUSY(device) (uint32_t)(CPAL_I2C_DEVICE[(device)]->ISR & I2C_ISR_BUSY)
546 #define __CPAL_I2C_HAL_CLEAR_ADDR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ADDRCF
548 #define __CPAL_I2C_HAL_CLEAR_NACK(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_NACKCF
550 #define __CPAL_I2C_HAL_CLEAR_STOP(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_STOPCF
552 #define __CPAL_I2C_HAL_CLEAR_BERR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_BERRCF
554 #define __CPAL_I2C_HAL_CLEAR_ARLO(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_ARLOCF
556 #define __CPAL_I2C_HAL_CLEAR_OVR(device) CPAL_I2C_DEVICE[(device)]->ICR = I2C_ICR_OVRCF
563 uint32_t I2C1_IRQHandler(
void);
568 uint32_t I2C2_IRQHandler(
void);
572 #ifdef CPAL_I2C_DMA_PROGMODEL
577 uint32_t CPAL_I2C1_DMA_IRQHandler(
void);
581 uint32_t CPAL_I2C2_DMA_IRQHandler(
void);
597 #ifdef CPAL_I2C_DMA_PROGMODEL